AD9540-VCO/PCBZ Analog Devices Inc, AD9540-VCO/PCBZ Datasheet - Page 22

• Manufacturer Part Number: AD9540-VCO/PCBZ
• Description: 650 MHz Clock Generator Eval Bd.
• Manufacturer: Analog Devices Inc

Specifications of AD9540-VCO/PCBZ

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9540
SERIAL PORT OPERATION
An AD9540 serial data port communication cycle has two
phases. Phase 1 is the instruction cycle, writing an instruction
byte to the AD9540, coincident with the first eight SCLK rising
edges. The instruction byte provides the AD9540 serial port
controller with information regarding the data transfer cycle,
which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines the serial address of the register being
accessed and whether the upcoming data transfer is read or
write.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9540. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9540
and the system controller.
.
SCLK
SDI/O
SCL K
SDI/O
SDO
CS
CS
SCL K
SDI/O
SCLK
SDI/O
CS
CS
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INSTRUCTION CYCLE
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INSTRUCTION CYCLE
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INSTRUCTION CYCLE
Figure 42. 2-Wire Serial Port Read Timing—Clock Stall High
INSTRUCTION CYCLE
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Figure 40. 3-Wire Serial Port Read Timing—Clock Stall Low
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Figure 41. Serial Port Write Timing—Clock Stall High
Figure 39. Serial Port Write Timing—Clock Stall Low
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Rev. A | Page 22 of 32
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The number of bytes transferred during Phase 2 of the commu-
nication cycle is a function of the register being accessed. For
example, when accessing Control Function Register 2, which is four
bytes wide, Phase 2 requires that four bytes be transferred. If
accessing a frequency tuning word, which is six bytes wide,
Phase 2 requires that six bytes be transferred. After transferring
all data bytes per the instruction, the communication cycle is
completed.
At the completion of any communication cycle, the AD9540
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9540 is registered on the rising edge of
SCLK. All data is driven out of the AD9540 on the falling edge
of SCLK. Figure 39 through Figure 42 are useful in understand-
ing the general operation of the AD9540 serial port.
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DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
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DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
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DON'T CARE
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