AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 47
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AD9522-5BCPZ
Manufacturer Part Number
AD9522-5BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-5BCPZ-REEL7.pdf
(76 pages)
Specifications of AD9522-5BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Ic Interface Type
I2C, SPI
Frequency
2.4GHz
No. Of Outputs
12
No. Of Multipliers / Dividers
4
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9522-5BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Data Transfer Format
Send byte format—the send byte protocol is used to set up the register address for subsequent commands.
S
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S
Read byte format—the combined format of the send byte and the receive byte.
S
I²C Serial Port Timing
Table 36. I2C Timing Definitions
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
I2C
IDLE
HLD; STR
SET; STR
SET; STP
HLD; DAT
SET; DAT
LOW
HIGH
RISE
FALL
SPIKE
Slave Address
Slave
Address
SDA
SCL
Slave Address
Slave Address
t
FALL
S
W
A
t
W
HLD; STR
t
LOW
RAM Address
High Byte
A
Description
I²C clock frequency
Bus idle time between stop and start conditions
Hold time for repeated start condition
Setup time for repeated start condition
Setup time for stop condition
Hold time for data
Setup time for data
Duration of SCL clock low
Duration of SCL clock high
SCL/SDA rise time
SCL/SDA fall time
Voltage spike pulse width that must be suppressed by the input filter
W
RAM Address
High Byte
R
t
t
RISE
SET; DAT
t
HLD; DAT
A
A
A
RAM Address High Byte
RAM Data 0
RAM Address
Low Byte
t
HIGH
A
RAM Address
Low Byte
t
FALL
Figure 48. I²C Serial Port Timing
Rev. 0 | Page 47 of 76
t
SET; STR
A
A
Sr
A
Slave
Address
Sr
RAM Data 1
RAM Data 0
t
HLD; STR
A
R
A
RAM Address Low Byte
A
RAM
Data 0
RAM Data 1
t
SPIKE
A
t
SET; STP
A
RAM Data 2
t
RISE
RAM
Data 1
P
A
t
IDLE
RAM Data 2
A
RAM
Data 2
AD9522-5
S
A
A
A
A
P
P
P
P