AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 25
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AD9522-5BCPZ
Manufacturer Part Number
AD9522-5BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-5BCPZ-REEL7.pdf
(76 pages)
Specifications of AD9522-5BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Ic Interface Type
I2C, SPI
Frequency
2.4GHz
No. Of Outputs
12
No. Of Multipliers / Dividers
4
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9522-5BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9522 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 43 to Table 54). Each section or function must be
individually programmed by setting the appropriate bits in the
corresponding control register or registers. When the desired
configuration is programmed, the user can store these values in
the on-board EEPROM to allow the part to power up in the
desired configuration without user intervention.
Mode 1: Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is <1600 MHz, a configuration that bypasses the
VCO divider can be used. This is the only difference from Mode 2.
Bypassing the VCO divider limits the frequency of the clock
source to <1600 MHz (due to the maximum input frequency
allowed at the channel dividers).
For clock distribution applications where the external clock is
<1600 MHz, the register settings shown in Table 19 should be used.
Table 19. Settings for Clock Distribution < 1600 MHz
Register
0x010[1:0] = 01b
0x1E1[0] = 1b
Description
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as the source for
the distribution section
Rev. 0 | Page 25 of 76
When using the PLL with an external VCO < 1600 MHz, the PLL
must be turned on.
Table 20. Settings for Using the PLL with External VCO <
1600 MHz
Register
0x1E1[0] = 1b
0x010[1:0] = 00b
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the VCO/
VCXO. This loop filter determines the loop bandwidth and stability
of the PLL. Make sure to select the proper PFD polarity for the
VCO/VCXO being used.
Table 21. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
Description
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control voltage
produces lower frequency)
Description
Bypass the VCO divider as the source for
the distribution section
PLL normal operation (PLL on) along
with other appropriate PLL settings in
0x010 to 0x01F
AD9522-5