AD9236BRUZ-80 Analog Devices Inc, AD9236BRUZ-80 Datasheet - Page 18

• Manufacturer Part Number: AD9236BRUZ-80
• Description: 12-BIT 3V 80 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9236BRUZ-80

• Number Of Bits: 12
• Sampling Rate (per Second): 80M
• Number Of Converters: 2
• Power Dissipation (max): 366mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Sampling Rate: 80MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 122mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9236
If the internal reference of the AD9236 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered.
how the internal reference voltage is affected by loading. A
2 mA load is the maximum recommended load.
External Reference Operation
The use of an external reference can be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a
single reference (internal or external) can be necessary to
reduce gain matching errors to an acceptable level. Figure 36
shows the typical drift characteristics of the internal reference
in both 1.0 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
–0.05
–0.10
–0.15
–0.20
–0.25
0.05
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–40 –30 –20 –10
0
Figure 35. VREF Accuracy vs. Load
0.5
Figure 36. Typical VREF Drift
0
1.0
V
TEMPERATURE (°C)
1.0V ERROR (%)
V
REF
REF
10
LOAD (mA)
= 0.5V
= 1.0V
20
1.5
30
40
0.5V ERROR (%)
2.0
Figure 35 depicts
50
60
2.5
70
03066-0-011
03066-0-019
80
3.0
Rev. B | Page 18 of 36
OPERATIONAL MODE SELECTION
As discussed in the Digital Outputs section, the AD9236 can
output data in either offset binary or twos complement format.
There is also a provision for enabling or disabling the clock duty
cycle stabilizer (DCS). The MODE pin is a multilevel input that
controls the data format and DCS state. The input threshold
values and corresponding mode selections are outlined in
Table 11. Mode Selection
MODE Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
EVALUATION BOARD
The AD9236 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
It is critical that signal sources with very low phase noise (< 1 ps
rms jitter) be used to realize the ultimate performance of the
converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
TSSOP Evaluation Board
Figure 37 shows the typical bench setup used to evaluate the ac
performance of the AD9236. The AD9236 can be driven single-
ended or differentially through an AD8138 driver or a
transformer. Separate power pins are provided to isolate the
DUT from the support circuitry. Each input configuration can
be selected by proper connection of various jumpers (refer to
the schematics).
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance (that is, IF undersampling
characterization). It allows the user to apply a clock input signal
that is 4× the target sample rate of the AD9236. A low jitter,
differential divide-by-4 counter, the MC100LVEL33D, provides
a 1× clock output that is subsequently returned back to the CLK
input via JP9. For example, a 260 MHz signal (sinusoid) is
divided down to a 65 MHz signal for clocking the ADC. Note
that R1 must be removed with the AUXCLK interface. Lower
jitter is often achieved with this interface since many RF signal
generators display improved phase noise at higher output
frequencies and the slew rate of the sinusoidal output signal is
4× that of a 1× signal of equal amplitude.
Data Format
Twos Complement
Twos Complement
Offset Binary
Offset Binary
Duty Cycle
Stabilizer
Disabled
Enabled
Enabled
Disabled
Table 11.