AD9236BRUZ-80 Analog Devices Inc, AD9236BRUZ-80 Datasheet
AD9236BRUZ-80
Specifications of AD9236BRUZ-80
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AD9236BRUZ-80 Summary of contents
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FEATURES Single 3 V supply operation (2 3.6 V) SNR = 70.4 dBc to Nyquist SFDR = 87.8 dBc to Nyquist Low power: 366 mW Differential input with 500 MHz bandwidth On-chip reference and sample-and-hold DNL = ±0.4 ...
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AD9236 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 5 Switching Specifications .................................................................. 6 ...
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DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS p-p differential input, 1.0 V external reference, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes 1 Offset Error Gain Error ...
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AD9236 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE-RATIO (SNR) f ...
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DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, 1.0 V external reference, unless otherwise noted. Table 3. Parameter LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current ...
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AD9236 SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period 1 CLK Pulse Width High 1 CLK Pulse Width Low DATA OUTPUT ...
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ABSOLUTE MAXIMUM RATINGS Table 6. With Parameter Respect to Min ELECTRICAL AVDD AGND –0.3 DRVDD DGND –0.3 AGND DGND –0.3 AVDD DRVDD –3 D11 DGND –0.3 CLK, MODE AGND –0.3 VIN+, VIN– AGND –0.3 VREF AGND –0.3 SENSE ...
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AD9236 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay ( The delay between the ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OTR 1 28 MODE 2 27 SENSE 3 26 VREF 4 25 REFB 5 24 REFT 6 23 AD9236 AVDD 7 22 TOP VIEW (Not to Scale) AGND 8 21 VIN VIN– 10 ...
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AD9236 EQUIVALENT CIRCUITS AVDD VIN+, VIN– Figure 5. Equivalent Analog Input Circuit AVDD MODE Figure 6. Equivalent MODE Input Circuit 03600-0-003 20kΩ 03600-0-004 Rev Page DRVDD D11-D0, OTR 03600-0-005 Figure 7. Equivalent Digital Output Circuit ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V, sample rate = 80 MSPS, DCS disabled, T VREF = 1.0 V external, unless otherwise noted. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...
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AD9236 0 AIN = –6.5dBFS –10 SNR = 71.3dBFS SFDR = 92.5dBc –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) Figure 15. Two-Tone 8K FFT @ 30 MHz and 31 ...
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INPUT FREQUENCY (MHz) Figure 21. SNR vs. Input Frequency 95 SFDR (DCS ON SFDR (DCS OFF) 80 SNR (DCS OFF ...
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AD9236 THEORY OF OPERATION The AD9236 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit ...
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The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: VREF = VCM MIN ...
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AD9236 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t ) can be calculated with the ...
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TIMING The AD9236 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. Refer to PD Figure 2 for a detailed ...
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AD9236 If the internal reference of the AD9236 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. how the internal reference voltage is affected by loading. A ...
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LFCSP Evaluation Board The typical bench setup used to evaluate the ac performance of the AD9236 is similar to the TSSOP evaluation board connections. The AD9236 can be driven single-ended or differentially through a transformer. Separate power pins are provided ...
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AD9236 Figure 38. TSSOP Evaluation Board Schematic, DUT Rev Page ...
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EJECTORS NO MALE ANGLE RIGHT 1N5712 1N5712 Figure 39. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering Rev Page HEADER AD9236 ...
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AD9236 Figure 40. TSSOP Evaluation Board Schematic, Analog Inputs Rev Page ...
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DACLK 1 28 MSB–DB11 CLOCK DD0 2 27 DD1 DB10 DVDD 3 26 DD2 DB19 DCOM 4 25 DD3 DB8 AD9762 NC3 5 24 DD4 DB7 AVDD 6 23 DD5 DB6 COMP2 7 22 DD6 DB5 IOUTA ...
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AD9236 Figure 43. TSSOP Evaluation Board Layout, Secondary Side Figure 44. TSSOP Evaluation Board Layout, Ground Plane Rev Page 03066-0-026 03066-0-027 ...
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Figure 45. TSSOP Evaluation Board Layout, Power Plane Figure 46. TSSOP Evaluation Board Layout, Primary Silkscreen Rev Page AD9236 03066-0-028 03066-0-029 ...
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AD9236 Figure 47. TSSOP Evaluation Board Layout, Secondary Silkscreen Rev Page 03066-0-030 ...
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P2 5.0V VAMP VDL 2.5V GND 2.5V DRVDD GND 3.0V AVDD D10 19 D11 20 OTR 21 MODE 22 SENSE 23 VREF 24 Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs and DUT Rev ...
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AD9236 Figure 49. LFCSP Evaluation Board Schematic, Digital Path Rev Page ...
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Figure 50. LFCSP Evaluation Board Schematic, Clock Input Rev Page AD9236 ...
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AD9236 Figure 51. LFCSP Evaluation Board Layout, Primary Side Figure 52. LFCSP Evaluation Board Layout, Secondary Side 03066-0-053 Figure 53. LFCSP Evaluation Board Layout, Ground Plane 03066-0-054 Figure 54. LFCSP Evaluation Board Layout, Power Plane Rev Page 30 ...
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Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev Page AD9236 03066-0-058 ...
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AD9236 Table 12. LFCSP Evaluation Board Bill of Materials 1 Item Qty. Omit Reference Designator 1 18 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C18, C27, C17, ...
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OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE ...
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... AD9236 ORDERING GUIDE Model Temperature Range AD9236BRU-80 –40°C to +85°C AD9236BRURL7-80 –40°C to +85°C 1 AD9236BRUZ-80 –40°C to +85°C 1 AD9236BRUZRL7-80 –40°C to +85°C 2 AD9236BCP-80 –40°C to +85°C 2 AD9236BCPRL7-80 –40°C to +85° AD9236BCPZ-80 –40°C to +85°C ...
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NOTES Rev Page AD9236 ...
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AD9236 NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03066-0-1/06(B) Rev Page ...