AD9236BRUZ-80 Analog Devices Inc, AD9236BRUZ-80 Datasheet - Page 16

• Manufacturer Part Number: AD9236BRUZ-80
• Description: 12-BIT 3V 80 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9236BRUZ-80

• Number Of Bits: 12
• Sampling Rate (per Second): 80M
• Number Of Converters: 2
• Power Dissipation (max): 366mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Sampling Rate: 80MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 122mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9236
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(f
following equation:
In the equation, the rms aperture jitter represents the root-
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter
(see Figure 31).
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the
AD9236. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 32, the power dissipated by the AD9236 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(I
where N is the number of output bits, 12 in the case of the
AD9236. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency, f
established by the average number of output bits switching,
INPUT
DRVDD
I
SNR
I
DRVDD
) due only to aperture jitter (t
DRVDD
) can be calculated as
75
70
65
60
55
50
45
40
=
= V
20
1
=
Figure 31. SNR vs. Input Frequency and Jitter
log
V
DRVDD
DRVDD
10
⎡
⎢
⎢
⎣
× C
2
π
×
f
CLK
LOAD
INPUT
C
INPUT FREQUENCY (MHz)
1
10
LOAD
/2. In practice, the DRVDD current is
× f
×
CLK
t
×
J
f
⎤
⎥
⎥
⎦
CLK
× N
J
) can be calculated with the
×
N
100
0.2ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
0.5ps
MEASURED
SNR
03066-0-043
1000
Rev. B | Page 16 of 36
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 32
was taken with the same operating conditions as the Typical
Performance Characteristics, and with a 5 pF load on each
output driver.
By asserting the PDWN pin high, the AD9236 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During
standby, the output drivers are placed in a high impedance
state. Reasserting the PDWN pin low returns the AD9236
to its normal operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
DIGITAL OUTPUTS
The AD9236 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies, which can affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts can require external buffers or latches.
As detailed in Table 11, the data format can be selected for
either offset binary or twos complement.
425
400
375
350
325
300
Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz
10
20
30
40
SAMPLE RATE (MSPS)
TOTAL POWER
ANALOG CURRENT
DIGITAL CURRENT
50
60
70
80
90
03066-0-044
100
140
120
100
80
60
40
20
0