AD73322LARUZ Analog Devices Inc, AD73322LARUZ Datasheet - Page 9

• Manufacturer Part Number: AD73322LARUZ
• Description: IC,PCM CODEC,DUAL,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARUZ

• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
Specifications subject to change without notice.
REV. B
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
SDOFS (O)
SCLK (O)
SDIFS (I)
SDO (O)
SDI (I)
SE (I)
THREE-
STATE
THREE-
STATE
THREE-
STATE
Figure 1. MCLK Timing
t
2
t
9
t
Limit at
T
61
24.4
24.4
t
0.4
0.4
20
0
10
10
10
10
30
1
1
A
= –40 C to +85 C
t
t
1
1
SCLK*
MCLK
t
3
(AVDD = +5 V
otherwise noted)
t
12
t
7
t
t
10
D15
13
t
8
Figure 4. Serial Port (SPORT)
t
* SCLK IS INDIVIDUALLY PROGRAMMABLE
11
IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
D15
t
1
10%; DVDD = +5 V
t
5
–9–
D14
t
4
t
2
D2
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
t
6
Figure 2. Load Circuit for Timing Specifications
D1
10%; AGND = DGND = 0 V; T
TO OUTPUT
t
D1
3
PIN
D0
15pF
t
7
C
D0
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
L
t
8
100 A
100 A
A
= T
I
I
OL
OH
MlN
to T
AD73322
MAX
+2.1V
D15
, unless
D15
D14