AD73322LARUZ Analog Devices Inc, AD73322LARUZ Datasheet - Page 14

• Manufacturer Part Number: AD73322LARUZ
• Description: IC,PCM CODEC,DUAL,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARUZ

• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD73322
FUNCTIONAL DESCRIPTION
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filter-
ing. Due to the high level of oversampling, the input antialias
requirements are reduced such that a simple single pole RC
stage is sufficient to give adequate attenuation in the band of
interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
REFCAP
REFOUT
VOUTN1
VOUTN2
VOUTP1
VOUTP2
VFBN1
VFBP1
VFBN2
VFBP2
VINN1
VINN2
VINP1
VINP2
V
V
REF
REF
+6/–15dB
+6/–15dB
ANALOG
ANALOG
PGA
PGA
LOOP
BACK
LOOP
BACK
AGND1
REFERENCE
CONTINUOUS
CONTINUOUS
LOW-PASS
LOW-PASS
FILTER
GAIN
FILTER
GAIN
AGND2
TIME
TIME
1
1
Figure 9. Functional Block Diagram
SINGLE-ENDED
SINGLE-ENDED
ENABLE
ENABLE
INVERT
INVERT
CAPACITOR
CAPACITOR
SWITCHED
LOW-PASS
SWITCHED
LOW-PASS
FILTER
FILTER
AVDD1
AD73322
0/38dB
0/38dB
–14–
PGA
PGA
AVDD2
1-BIT
1-BIT
DAC
DAC
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
IGS2
0
0
0
0
1
1
1
1
MODULATOR
MODULATOR
DIGITAL
DIGITAL
SIGMA-DELTA
SIGMA-DELTA
Table IV. PGA Settings for the Encoder Channel
SIGMA-
SIGMA-
MODULATOR
MODULATOR
DELTA
DELTA
ANALOG
ANALOG
IGS1
0
0
1
1
0
0
1
1
DGND
GAIN
GAIN
1
1
DECIMATOR
DECIMATOR
POLATOR
POLATOR
INTER-
INTER-
DVDD
IGS0
0
1
0
1
0
1
0
1
SERIAL
PORT
I/O
Gain (dB)
0
6
12
18
20
26
32
38
SDI
SDIFS
SCLK
RESET
MCLK
SE
SDO
SDOFS
REV. B