AD73322LARUZ Analog Devices Inc, AD73322LARUZ Datasheet - Page 16

• Manufacturer Part Number: AD73322LARUZ
• Description: IC,PCM CODEC,DUAL,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARUZ

• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD73322
Decimation Filter
The digital filter used in the AD73322 carries out two important
functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high frequency bit-stream to a lower rate 16-bit
word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits or greater
(depending on chosen sampling rate). Its Z transform is given
as:
where N is set by the sampling rate (N = 32 @ 64 kHz sampling
. . . N = 256 @ 8 kHz sampling). Thus when the sampling rate
is 64 kHz, a minimal group delay of 25 s can be achieved.
Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
sigma-delta modulator and decimator output equals 32, there
are five bits per stage of the three-stage Sinc3 filter. Due to
symmetry within the sigma-delta modulator, the LSB will al-
ways be a zero; therefore, the 16-bit ADC output word will have
2 LSBs equal to zero, one due to the sigma-delta symmetry and
the other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in
transferring the decimator output as the ADC word. For example,
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator output.
This yields eight bits per stage of the three-stage Sinc3 filter.
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 12). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a word length of up to 24 bits
(depending on decimation rate chosen), which is the final out-
put of the ADC block. In Data Mode this value is truncated to
16 bits for output on the Serial Data Output (SDO) pin.
ANALOG
ANALOG
INPUT
INPUT
V
V
V
V
REF
REF
Figure 12. ADC Transfer Function
REF
REF
+ (V
– (V
+ (V
– (V
REF
REF
REF
REF
[(1 – Z
0.32875)
0.32875)
0.6575)
0.6575)
V
REF
10...00
–N
10...00
)/(1 – Z
ADC CODE DIFFERENTIAL
ADC CODE SINGLE-ENDED
V
INN
V
V
V
INN
INP
INP
–1
00...00
00...00
)]
3
01...11
01...11
–16–
In mixed Control/Data Mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.
Decoder Channel
The decoder channels consist of digital interpolators, digital
sigma-delta modulators, single-bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain ampli-
fiers with differential outputs.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital filter
that up-samples the 16-bit input words from the input sample
rate to a rate of DMCLK/8, while filtering to attenuate images
produced by the interpolation process. Its Z transform is given as:
where N is determined by the sampling rate (N = 32 @
64 kHz . . . N = 256 @ 8 kHz). The DAC receives 16-bit
samples from the host DSP processor at the programmed
sample rate of DMCLK/N. If the host processor fails to write a
new value to the serial port, the existing (previous) data is read
again. The data stream is filtered by the anti-imaging interpola-
tion filter, but there is an option to bypass the interpolator for
the minimum group delay configuration by setting the IBYP bit
(CRE:5) of Control register E. The interpolation filter has the
same characteristics as the ADC’s antialiasing decimation filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized in
the passband of the converter. The bit-stream output of the
sigma-delta modulator is fed to the single-bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGA
The output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB to
+6 dB in 3 dB steps, as shown in Table V. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
OGS2
0
0
0
0
1
1
1
1
Table V. PGA Settings for the Decoder Channel
OGS1
0
0
1
1
0
0
1
1
[(1 – Z
–N
)/(1 – Z
OGS0
0
1
0
1
0
1
0
1
–1
)]
3
Gain (dB)
+6
+3
0
–3
–6
–9
–12
–15
REV. B