AD5612YKSZ-2REEL7 Analog Devices Inc, AD5612YKSZ-2REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD5612YKSZ-2REEL7
• Description: IC,D/A CONVERTER,SINGLE,10-BIT,CMOS,TSSOP,6PIN
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5612YKSZ-2REEL7

• Settling Time: 6µs
• Number Of Bits: 10
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 500µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
t
t
t
t
t
t
t
1
2
3
4
TIMING DIAGRAM
8
9
10
11
11A
12
SP
See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the
AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2.
C
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
B
4
refers to the capacitance on the bus line.
Conditions
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, C
High speed mode, C
Standard mode
Fast mode
High speed mode, C
High speed mode, C
Standard mode
Fast mode
High speed mode, C
High speed mode, C
Standard mode
Fast mode
High speed mode, C
High speed mode, C
Standard mode
Fast mode
High speed mode, C
High speed mode, C
Fast mode
High speed mode
SDA
SCL
P
t
7
2
S
B
B
B
B
B
B
B
B
B
B
t
t
6
= 100 pF
= 400 pF
= 100 pF
= 400 pF
= 100 pF
= 400 pF
= 100 pF
= 400 pF
= 100 pF
= 400 pF
2
t
4
t
11
Figure 2. 2-Wire Serial Interface Timing Diagram
Min
4
0.6
160
10
20
10
20
10
20
10
20
10
20
0
0
Limit at T
t
Rev. B | Page 5 of 24
3
t
1
t
12
MIN
, T
Max
1000
300
80
160
300
300
80
160
1000
300
40
80
1000
300
80
160
300
300
40
80
50
10
MAX
S
t
Unit
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
5
10
t
6
Description
t
t
t
t
t
condition and after an acknowledge bit
t
Pulse width of spike suppressed
SU;STO
RDA
FDA
RCL
RCL1
FCL
, fall time of SCL signal
, rise time of SCL signal
, fall time of SDA signal
, rise time of SDA signal
, rise time of SCL signal after a repeated start
, setup time for a stop condition
AD5602/AD5612/AD5622
t
8
P
t
9