A6280EA-T Allegro Microsystems Inc, A6280EA-T Datasheet - Page 6

• Manufacturer Part Number: A6280EA-T
• Description: IC,Laser Diode/LED Driver,DIP,16PIN,PLASTIC
• Manufacturer: Allegro Microsystems Inc
• Type: PWM Controlr

Specifications of A6280EA-T

• Constant Current: Yes
• Topology: Linear, PWM
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Secondary: RGB
• Frequency: 5MHz
• Voltage - Supply: 4.75 V ~ 17 V
• Voltage - Output: 1 V ~ 3 V
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 150mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1256

A6280
Shift Register
The A6280 has a 31 bit shift register that loads data through the
SDI (Serial Data In) pin. The shift register operates by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 30)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of
the CI (Clock In) pin. The SDO (Serial Data Out) pin is updated
to the state of bit 30 on the falling edge of the CI pin. This will
prevent any race conditions and erroneous data that might occur
while propagating information through multiple A6280 that are
daisy chained together. The contents of the shift register will
continue to propagate on every rising edge of the CI pin. The
information in the shift register is latched on a rising edge of the
LI (Latch In) pin. The LI pin must be brought low before the ris-
ing edge of the next clock pulse, to avoid latching erroneous data.
The latched data remains latched on a rising OEI (Output Enable
In) signal.
Output Buffers
The A6280 is designed to allow daisy chaining many A6280s
together. It can pass the clock, data, latch, and output enable
R
EXT
VREG
REXT
OEI
SDI
VIN
CI
LI
Regulator
+5 V
Scalar 0
Shift Register
Latched Registers
Current
0 to 6
7 Bits
PWM Counter 0
Regulator 0
Current
Divider
10 Bits
Clock
2 Bits
7 to 8
OUT0
Functional Description
Unused
Figure 4. Functional Diagram
1 Bit
9
3-Channel Constant-Current LED Driver
Scalar 1
10 to 16
Current
7 Bits
PWM Counter 1
Regulator 1
Current
10 Bits
OUT1
with
signals from one A6820 to the next without any loss of data due
to duty cycle skewing or signal degradation.
The A6820 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6280s
without the need for extra driving hardware. The A6280 drives
these signals to TTL levels. Each of the A6280 inputs have a cor-
responding buffered output:
• CI (Clock In) pin to CO (Clock Out) pin
• LI (Latch In) pin to LO (Latch Out) pin
• OEI (Output Enable In) pin to OEO (Output Enable Out) pin
• SDI (Serial Data In) pin to SDO (Serial Data Out) pin
The CO (Clock Out) pin is driven by an internal one-shot circuit.
When the CI pin detects an edge rising through the input thresh-
old, the one-shot circuitry drives the CO pin high for 100 ns. The
CI pin input threshold has hysteresis to prevent false triggering
of the CO signal. The implementation on the one-shot solution
allows many A6280s to be daisy chained together with a consis-
tent clock signal throughout the entire chain without degradation
or loss of synchronicity to the data line.
Unused
17 to 19
3 Bits
Scalar 2
20 to 26
Current
7 Bits
Programmable
PWM Counter 2
Regulator 2
Unused
Current
10 Bits
1 Bit
27
OUT2
28 to 29
2 Bits
Test
Bits
One-Shot
100 ns
PGND
Bit 30
Bit 30
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
30
“1”
“0”
LGND
PWM Control
SDO
CO
LO
OEO
6