A6280EA-T Allegro Microsystems Inc, A6280EA-T Datasheet - Page 10

• Manufacturer Part Number: A6280EA-T
• Description: IC,Laser Diode/LED Driver,DIP,16PIN,PLASTIC
• Manufacturer: Allegro Microsystems Inc
• Type: PWM Controlr

Specifications of A6280EA-T

• Constant Current: Yes
• Topology: Linear, PWM
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Secondary: RGB
• Frequency: 5MHz
• Voltage - Supply: 4.75 V ~ 17 V
• Voltage - Output: 1 V ~ 3 V
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 150mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1256

A6280
Timing Considerations
A6280s can be used in large numbers to drive many LEDs with
the control signals connected serially together, with short cables
between each pixel (see figure 8). Because the clock negative
edge drives the data to the SDO (Serial Data Out) pin, and the
CO pin is driven by a 100 ns one-shot function, the clock and
data signals remain synchronized with each other as you move
from the first pixel in the chain to the last.
After all of the data is written to each A6280 in the chain, the
data is latched into each A6280 via a low-to-high transition on
the LI pin. The LO pin of pixel #1 drives the LI pin of pixel #2,
and so on down the chain. These signals are buffered and are
driven asynchronously relative to the CI and SDI pins. Therefore
the mismatch in delays between CO and LO must be taken into
consideration.
CO(n-1) = CI(n)
LO(n-1) = LI (n)
CO(1) = CI(2)
CO(2) = CI(3)
LO(1) = LI (2)
LO(2) = LI (3)
Figure 7. Signal Delay Mismatch Timing Diagram. t
LI) applied to the first pixel in the chain. Note the difference in delay for CI(1) to CI(n)
compared to the delay for LI(1) to LI(n). This must be compensated by increasing t
CI(1)
LI (1)
Application Information
3-Channel Constant-Current LED Driver
with
Although the mismatches in delays are quite small, they must be
considered when creating the timing pattern for driving the chain.
The key parameter is the setup time from the last CI clock rising
edge to the rising edge of LI.
The minimum A6280 setup time from CI to LI is 20 ns. There
may be a 5 ns per pixel mismatch in the propagation delays of the
CI and LI signals (the delay from CI to CO compared to the delay
from LI to LO). As a rule of thumb, use a setup time, t
first A6280 in the chain as calculated below:
where n is the number of pixels in the chain.
This will ensure that the setup time at the last pixel in the chain is
at least 20 ns.
su
is the setup time for signals (CI to
Programmable
CI(1) to CI(n)
t
su
t
su
= 20 ns + n × 5 ns ,
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
su
.
LI(1) to LI(n)
PWM Control
su
, at the
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