EVAL-ADAU1761Z Analog Devices Inc, EVAL-ADAU1761Z Datasheet - Page 86

• Manufacturer Part Number: EVAL-ADAU1761Z
• Description: Eval Board For ADAU1761
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r

Specifications of EVAL-ADAU1761Z

• Main Purpose: Audio, CODEC
• Embedded: Yes, DSP
• Utilized Ic / Part: ADAU1761
• Primary Attributes: Stereo, 24-Bit, 8 ~ 96 kHz Sampling Rate, GUI Tool
• Secondary Attributes: I²C and GPIO Interfaces, 2 Differential and 1 Stereo Single-Ended Analog Inputs and Outputs
• Silicon Manufacturer: Analog Devices
• Core Architecture: SigmaDSP
• Silicon Core Number: ADAU1761
• Silicon Family Name: SigmaDSP
• Application Sub Type: Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1761
R65: Clock Enable 0, 16,633 (0x40F9)
This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this
register to disable blocks that are not being used.
Bit 7
Reserved
Table 90. Clock Enable 0 Register
Bits
6
5
4
3
2
1
0
R66: Clock Enable 1, 16,634 (0x40FA)
This register enables Digital Clock Generator 0 and Digital Clock Generator 1. Digital Clock Generator 0 generates sample rates for the
ADCs, DACs, and DSP. Digital Clock Generator 1 generates BCLK and LRCLK for the serial port when the part is in master mode. For
maximum power saving, use this register to disable clocks that are not being used.
Bit 7
Table 91. Clock Enable 1 Register
Bits
1
0
Bit Name
SLEWPD
ALCPD
DECPD
SOUTPD
INTPD
SINPD
SPPD
Bit Name
CLK1
CLK0
Bit 6
SLEWPD
Bit 6
Description
Codec slew digital clock engine enable. When powered down, the analog playback path volume controls are
disabled and stay set to their current state.
0 = powered down (default).
1 = enabled.
ALC digital clock engine enable.
0 = powered down (default).
1 = enabled.
Decimator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
Serial routing outputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
Interpolator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
Serial routing inputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
Serial port digital clock engine enable.
0 = powered down (default).
1 = enabled.
Description
Digital Clock Generator 1.
0 = off (default).
1 = on.
Digital Clock Generator 0.
0 = off (default).
1 = on.
Bit 5
ALCPD
Bit 5
Reserved
Bit 4
DECPD
Bit 4
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Bit 3
SOUTPD
Bit 3
Bit 2
INTPD
Bit 2
Bit 1
SINPD
Bit 1
CLK1
Bit 0
SPPD
Bit 0
CLK0