EVAL-ADAU1761Z Analog Devices Inc, EVAL-ADAU1761Z Datasheet - Page 83

• Manufacturer Part Number: EVAL-ADAU1761Z
• Description: Eval Board For ADAU1761
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r

Specifications of EVAL-ADAU1761Z

• Main Purpose: Audio, CODEC
• Embedded: Yes, DSP
• Utilized Ic / Part: ADAU1761
• Primary Attributes: Stereo, 24-Bit, 8 ~ 96 kHz Sampling Rate, GUI Tool
• Secondary Attributes: I²C and GPIO Interfaces, 2 Differential and 1 Stereo Single-Ended Analog Inputs and Outputs
• Silicon Manufacturer: Analog Devices
• Core Architecture: SigmaDSP
• Silicon Core Number: ADAU1761
• Silicon Family Name: SigmaDSP
• Application Sub Type: Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R58: Serial Input Route Control, 16,626 (0x40F2)
Bit 7
Table 83. Serial Input Route Control Register
Bits
[3:0]
R59: Serial Output Route Control, 16,627 (0x40F3)
Bit 7
Table 84. Serial Output Route Control Register
Bits
[3:0]
Bit Name
SINRT[3:0]
Bit Name
SOUTRT[3:0]
Bit 6
Bit 6
Description
Serial data input routing. This register sets the input where the DACs receive serial data. This location can be
from the DSP or from any TDM slot on the serial port.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Serial data output routing. This register sets the output where the ADCs send serial data. This location can be to
the DSP or to any TDM slot on the serial port.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reserved
Reserved
Bit 5
Bit 5
Bit 4
Bit 4
Routing
DSP to DACs [L, R] (default)
Serial input [L0, R0] to DACs [L, R]
Reserved
Serial input [L1, R1] to DACs [L, R]
Reserved
Serial input [L2, R2] to DACs [L, R]
Reserved
Serial input [L3, R3] to DACs [L, R]
Reserved
Serial input [R0, L0] to DACs [L, R]
Reserved
Serial input [R1, L1] to DACs [L, R]
Reserved
Serial input [R2, L2] to DACs [L, R]
Reserved
Serial input [R3, L3] to DACs [L, R]
Routing
ADCs [L, R] to DSP (default)
ADCs [L, R] to serial output [L0, R0]
Reserved
ADCs [L, R] to serial output [L1, R1]
Reserved
ADCs [L, R] to serial output [L2, R2]
Reserved
ADCs [L, R] to serial output [L3, R3]
Reserved
ADCs [L, R] to serial output [R0, L0]
Reserved
ADCs [L, R] to serial output [R1, L1]
Reserved
ADCs [L, R] to serial output [R2, L2]
Reserved
ADCs [L, R] to serial output [R3, L3]
Rev. C | Page 83 of 92
Bit 3
Bit 3
Bit 2
Bit 2
SOUTRT[3:0]
SINRT[3:0]
Bit 1
Bit 1
ADAU1761
Bit 0
Bit 0