MFRC52201HN1 NXP Semiconductors, MFRC52201HN1 Datasheet - Page 92

• Manufacturer Part Number: MFRC52201HN1
• Description: RFID Modules & Development Tools CL READER IC'S
• Manufacturer: NXP Semiconductors

Specifications of MFRC52201HN1

• Data Rate: 3.4 Mbps
• Operating Temperature Range: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MFRC52201HN1,157

NXP Semiconductors
Table 69. RxThresholdReg register (address 18h); reset
Table 70. RxThresholdReg register bit descriptions . . . .51
Table 71. DemodReg register (address 19h); reset value:
Table 72. DemodReg register bit descriptions . . . . . . . . .51
Table 73. Reserved register (address 1Ah); reset value:
Table 74. Reserved register bit descriptions . . . . . . . . . .52
Table 75. Reserved register (address 1Bh); reset value:
Table 76. Reserved register bit descriptions . . . . . . . . . .52
Table 77. MfTxReg register (address 1Ch); reset value:
Table 78. MfTxReg register bit descriptions . . . . . . . . . .52
Table 79. MfRxReg register (address 1Dh); reset value:
Table 80. MfRxReg register bit descriptions . . . . . . . . . .53
Table 81. Reserved register (address 1Eh); reset value:
Table 82. Reserved register bit descriptions . . . . . . . . . .53
Table 83. SerialSpeedReg register (address 1Fh); reset
Table 84. SerialSpeedReg register bit descriptions . . . .53
Table 85. Reserved register (address 20h); reset value:
Table 86. Reserved register bit descriptions . . . . . . . . . .54
Table 87. CRCResultReg (higher bits) register (address
Table 88. CRCResultReg register higher bit descriptions . .
Table 89. CRCResultReg (lower bits) register (address
Table 90. CRCResultReg register lower bit descriptions .54
Table 91. Reserved register (address 23h); reset value:
Table 92. Reserved register bit descriptions . . . . . . . . . .55
Table 93. ModWidthReg register (address 24h);
Table 94. ModWidthReg register bit descriptions . . . . . .55
Table 95. Reserved register (address 25h); reset value:
Table 96. Reserved register bit descriptions . . . . . . . . . .55
Table 97. RFCfgReg register (address 26h); reset value:
Table 98. RFCfgReg register bit descriptions . . . . . . . . .56
Table 99. GsNReg register (address 27h); reset value:
Table 100.GsNReg register bit descriptions . . . . . . . . . . .56
Table 101.CWGsPReg register (address 28h); reset value:
MFRC522_33
Product data sheet
PUBLIC
value: 84h bit allocation . . . . . . . . . . . . . . . . . .51
4Dh bit allocation . . . . . . . . . . . . . . . . . . . . . . .51
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .52
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .52
62h bit allocation . . . . . . . . . . . . . . . . . . . . . . .52
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53
value: EBh bit allocation . . . . . . . . . . . . . . . . .53
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .54
21h); reset value: FFh bit allocation . . . . . . . . .54
54
22h); reset value: FFh bit allocation . . . . . . . . .54
88h bit allocation . . . . . . . . . . . . . . . . . . . . . . .55
reset value: 26h bit allocation . . . . . . . . . . . . .55
87h bit allocation . . . . . . . . . . . . . . . . . . . . . . .55
48h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
88h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . .57
Rev. 3 — 26 October 2009
112133
Table 102.CWGsPReg register bit descriptions . . . . . . . . 57
Table 103.ModGsPReg register (address 29h);
Table 104.ModGsPReg register bit descriptions . . . . . . . 57
Table 105.TModeReg register (address 2Ah); reset value:
Table 106.TModeReg register bit descriptions . . . . . . . . 58
Table 107.TPrescalerReg register (address 2Bh); reset
Table 108.TPrescalerReg register bit descriptions . . . . . 58
Table 109.TReloadReg (higher bits) register (address
Table 110.TReloadReg register higher bit descriptions . . 59
Table 111.TReloadReg (lower bits) register (address 2Dh);
Table 112.TReloadReg register lower bit descriptions . . 59
Table 113.TCounterValReg (higher bits) register
Table 114.TCounterValReg register higher bit descriptions .
Table 115.TCounterValReg (lower bits) register (address
Table 116.TCounterValReg register lower bit
Table 117.Reserved register (address 30h); reset value:
Table 118.Reserved register bit descriptions . . . . . . . . . . 60
Table 119.TestSel1Reg register (address 31h);
Table 120.TestSel1Reg register bit descriptions . . . . . . . 60
Table 121.TestSel2Reg register (address 32h);
Table 122.TestSel2Reg register bit descriptions . . . . . . . 61
Table 123.TestPinEnReg register (address 33h);
Table 124.TestPinEnReg register bit descriptions . . . . . . 61
Table 125.TestPinValueReg register (address 34h);
Table 126.TestPinValueReg register bit descriptions . . . . 62
Table 127.TestBusReg register (address 35h); reset value:
Table 128.TestBusReg register bit descriptions . . . . . . . . 62
Table 129.AutoTestReg register (address 36h);
Table 130.AutoTestReg register bit descriptions . . . . . . . 63
Table 131.VersionReg register (address 37h); reset value:
Table 132.VersionReg register bit descriptions . . . . . . . . 63
Table 133.AnalogTestReg register (address 38h); reset
Table 134.AnalogTestReg register bit descriptions . . . . . 64
reset value: 20h bit allocation . . . . . . . . . . . . . 57
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 57
value: 00h bit allocation . . . . . . . . . . . . . . . . . . 58
2Ch); reset value: 00h bit allocation . . . . . . . . 59
reset value: 00h bit allocation . . . . . . . . . . . . . 59
(address 2Eh); reset value: xxh bit allocation . 59
59
2Fh); reset value: xxh bit allocation . . . . . . . . . 59
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 60
reset value: 00h bit allocation . . . . . . . . . . . . . 60
reset value: 00h bit allocation . . . . . . . . . . . . . 60
reset value: 80h bit allocation . . . . . . . . . . . . . 61
reset value: 00h bit allocation . . . . . . . . . . . . . 61
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 62
reset value: 40h bit allocation . . . . . . . . . . . . . 62
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
value: 00h bit allocation . . . . . . . . . . . . . . . . . . 63
Contactless reader IC
MFRC522
© NXP B.V. 2009. All rights reserved.
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