ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 219

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.18.3
4921E–AUTO–09/09
SPI Data Modes and Timing
Table 4-83.
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and
UCPHAn functionality is summarized in
these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 4-84.
Figure 4-76. UCPHAn and UCPOLn Data Transfer Timing Diagrams
Operating Mode
Synchronous Master
mode
UCPOLn
BAUD
f
UBRRn
OSC
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Data setup (TXD)
Data sample (RXD)
Figure 4-76 on page
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
UCPHAn
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
0
1
UCPOL=0
Equation for Calculating Baud
BAUD
219. Data bits are shifted out and latched in on opposite edges of
SPI Mode
=
0
1
2
3
Rate
-------------------------------------- -
2 UBRRn
Table
(1)
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
4-84. Note that changing the setting of any of
+
1
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
ATA6602/ATA6603
Equation for Calculating UBRRn
UBRRn
Sample (Falling)
Trailing Edge
Setup (Falling)
Setup (Rising)
Sample (Rising)
UCPOL=1
Value
=
------------------- - 1
2BAUD
f
OSC
–
219