ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 106

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.10.4.8
4.10.4.9
4.11
106
External Interrupts
ATA6602/ATA6603
The Port D Data Direction Register – DDRD
The Port D Input Pins Address – PIND
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins
are configured as outputs. This feature provides a way of generating a software interrupt. The
pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change
interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0
will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-
ters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Register A – EICRA.
When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-
rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge
interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
and their Distribution” on page
nously. This implies that this interrupt can be used for waking the part also from sleep modes
other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
Initial Value
Read/Write
Initial Value
Read/Write
“System Clock and Clock Options” on page
Bit
Bit
PIND7
DDD7
R/W
N/A
R
7
0
7
PIND6
DDD6
R/W
N/A
R
6
6
0
49. Low level interrupt on INT0 and INT1 is detected asynchro-
PIND5
DDD5
R/W
N/A
R
5
5
0
PIND4
DDD4
R/W
N/A
R
4
4
0
49.
PIND3
DDD3
R/W
N/A
R
3
3
0
PIND2
DDD2
R/W
N/A
R
2
2
0
PIND1
DDD1
R/W
N/A
R
1
1
0
PIND0
DDD0
“Clock Systems
R/W
N/A
4921E–AUTO–09/09
R
0
0
0
DDRD
PIND