LFXP2-17E-L-EV Lattice, LFXP2-17E-L-EV Datasheet - Page 7

• Manufacturer Part Number: LFXP2-17E-L-EV
• Description: MCU, MPU & DSP Development Tools LatticeXP2 EVAL BRD STD
• Manufacturer: Lattice

Specifications of LFXP2-17E-L-EV

• Processor To Be Evaluated: LatticeXP2-17 FPGA
• Interface Type: RS-232, USB
• Silicon Manufacturer: Lattice
• Core Architecture: FlexiFLASH
• Silicon Core Number: LFXP2-17E-4F484C
• Silicon Family Name: LatticeXP2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The JTAG port is used for programming the LatticeXP2 and can also be used for programming the off-chip SPI
PROM. The LatticeXP2 FPGA has several modes it can use to get configuration data. Available sources for config-
uration data are:
• JTAG programming
• On-chip Flash PROM (with automatic failsafe)
• Off-chip SPI PROM (LatticeXP2 fetches configuration data)
• Off-chip SPI interface (LatticeXP2 receives configuration data from a master)
The JTAG interface to the LatticeXP2 provides several methods to program the LatticeXP2 and devices attached to
the LatticeXP2. JTAG programming can be used to program the LatticeXP2 in SRAM mode (volatile). It can also be
used to program the on-chip LatticeXP2 Flash memory (non-volatile). It also provides the ability to program an
attached SPI PROM (U5). The SPI PROM is used for storing failsafe configuration data.
ispPAC-POWR607 JTAG Access
The ispPAC-POWR607 Power Manager comes from the factory with a default power sequence. It may be desired
for evaluation purposes to try other power sequences. Connector J5 is the access point for the ispPAC-POWR607
JTAG I/O. See the Power Supplies and Supply Control section below for the details of using the ispPAC-POWR607.
SPI Slave Connection
The LatticeXP2 has configuration pins that define how the device will find a non-volatile bitstream to configure
itself. In most cases the configuration pins will be set to have the LatticeXP2 act as a master device and actively
read data from its internal Flash or from the attached SPI PROM.
The LatticeXP2 can also be configured to act as a slave device, and accept bitstream data from an external master.
The master can be connected to either the JTAG port, or it can be connected to the SPI interface. The LatticeXP2
Standard Evaluation Board provides a 1x10 header, J11, that permits an off-chip SPI master to program the
LatticeXP2 FPGA.
MachXO JTAG Connection
The MachXO’s primary function is to be the USB download cable interface for the LatticeXP2. However, the
MachXO is a PLD, and has some connections to the LatticeXP2. It is possible, therefore, to use the LatticeXP2 and
the MachXO together. The MachXO can be reprogrammed with custom logic using connector J23. The factory pro-
gram for the MachXO is available on-line to restore the device if needed.
LatticeXP2 and Support Interfaces
The LatticeXP2 Standard Evaluation Board provides a variety of support features for evaluating the performance
and functionality of the LatticeXP2 FPGA. A FPGA can be used for a large number of different applications. The
LatticeXP2 Standard Evaluation Board attempts to balance the ability to test I/O and the ability to use interest-
ing/common logic functions.
The evaluation board has features designed to make it easier to locate resources on the board and resources con-
nected to the FPGA.
• Devices are numbered in a consistent fashion. Each device starts at reference designator ‘1’ in the northwest
• Adjacent to most of the switch inputs, LED outputs, SMA connectors, and test points is the alphanumeric position
• SMA connectors have an open white rectangle area near them denoting the positive side of a matched pair. The
corner of the board (i.e. R1, C1, U1, L1...). The component number increases by one in a columnar fashion (i.e.
southward). When the south edge of the board is reached, the count resumes slightly east, and at the north side
of the board. Thus, the highest numbered components will always be in the southeast corner of the board. This
same numbering sequence is applied to the secondary side of the printed-circuit board.
of the pin on the LatticeXP2 FPGA. For example: next to the SMA connector J1, in the silkscreen, is the designa-
tor (P1). Thus LatticeXP2 (U7) pin P1 is connected to the center post of J1.
negative side of the matched pair has a solid filled white rectangular area.
7
Evaluation Board User’s Guide
LatticeXP2 Standard