LFXP2-17E-L-EV Lattice, LFXP2-17E-L-EV Datasheet - Page 10

• Manufacturer Part Number: LFXP2-17E-L-EV
• Description: MCU, MPU & DSP Development Tools LatticeXP2 EVAL BRD STD
• Manufacturer: Lattice

Specifications of LFXP2-17E-L-EV

• Processor To Be Evaluated: LatticeXP2-17 FPGA
• Interface Type: RS-232, USB
• Silicon Manufacturer: Lattice
• Core Architecture: FlexiFLASH
• Silicon Core Number: LFXP2-17E-4F484C
• Silicon Family Name: LatticeXP2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3. Oscillator Positions
The output from the oscillator is routed to two series resistors. One of the series resistors is connected to a primary
clock input pin. The other resistor is connected to a PLL input pin. It is important to mention that DIP socket pin 8 is
shorted to pin 11, so it is not possible to input two different clock frequencies from the socket. In order to provide a
frequency on the primary clock input that is different from the PLL clock input it is necessary to remove one of the
two series termination resistors, and add a temporary modification to inject an electrically isolated clock signal.
Differential/50 Ohm Input/Output
The LatticeXP2 Standard Evaluation Board provides connections to differential I/O pins. The circuit board traces for
these connections are nominally 50-ohm impedance. Some of the differential I/O pins are inputs to primary or PLL
clock drivers. If the built-in oscillator in socket XU1 does not provide the right kind of input clock the SMA connec-
tors listed in Table 9 can be used to provide additional reference clock frequencies.
Table 9. Differential/50 Ohm Trace Pin Assignments
Power Supplies and Supply Control
The LatticeXP2 Standard Evaluation Board operates from a 5V DC input voltage. The input voltage is supplied via
J9, a coaxial DC input jack. The following components operate using the 5V input:
• ispPAC-POWR607 Power Manager
• Bellnix DC/DC converters
Connector Pair
Pin 1
J10
J24
J25
J26
J27
J1
J2
J3
J4
J6
J7
J8
Full-Size Placement
Physical connection
Silkscreen text
Physical connection
Silkscreen text
Physical connection Y5 (3) / W4 (4)
Silkscreen text
OSC
LatticeXP2 I/O
T2 (3) / R2 (4)
10
K22
K21
L21
J22
R1
P1
P2
P3
U1 (3) / T1 (4)
Half-Size Placement
OSC
W4
T1
U1
Y5
Evaluation Board User’s Guide
Clock Input
Y (N)
Y (N)
Y (N)
Y (P)
Y (P)
Y (P)
N
N
N
N
N
N
LatticeXP2 Standard