71M6521DEIM-DB Maxim Integrated Products, 71M6521DEIM-DB Datasheet - Page 108

• Manufacturer Part Number: 71M6521DEIM-DB
• Description: Power Management Modules & Development Tools 71M6521DE DEMO BOARD M6521DE DEMO BOARD
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521DEIM-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7
Register
DIO0
DIO8
DIO9
DIO10
DIO11
DIO12
ERASE
PGADDR
EEDATA
EECTRL
FLSHCRL
Special Function Registers Specific to the 652X
DIO_0
DIO_DIR0
DIO_1
DIO_DIR1
DIO_2
DIO_DIR2
FLSH_ERASE
FLSH_PGADR
Alternative
Name
Address
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
0xA2
0xA0
0xA1
0xB7
0x9E
0xB2
0x80
0x90
0x91
0x94
0x9F
SFR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
TERIDIAN Proprietary
Description
Register for port 0 read and write operations (pins DIO0…DIO7)
Data direction register for port 0. Setting a bit to 1 means that the
corresponding pin is an output.
Register for port 1 read and write operations (pins DIO8…DIO15)
Data direction register for port 1. Setting a bit to 1 means that the
corresponding pin is an output.
Register for port 2 read and write operations (pins DIO16…DIO21)
Data direction register for port 2. Setting a bit to 1 means that the
corresponding pin is an output.
This register is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle (default
= 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write
Any other pattern written to FLSH_ERASE will have no effect.
Flash Page Erase Address register containing the flash memory page
address (page 0 thru 127) that will be erased during the Page Erase
cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
I2C EEPROM interface data register
I2C EEPROM interface control register. If the MPU wishes to write a
byte of data to EEPROM, it places the data in EEDATA and then
writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates
the transmit.
This multi-purpose register contains the following bits:
Bit 0 (FLSH_PWE): Program Write Enable:
(default).
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
0 – MOVX commands refer to XRAM Space, normal operation
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
a write to FLSH_PGADR @ SFR 0xB7.
to FLSH_MEEN @ sfr 0xB2 and the debug (CC) port must
be enabled.
71M652X Software User’s Guide
108 of 138