PAC-SYSTEMCLK5520 Lattice, PAC-SYSTEMCLK5520 Datasheet - Page 23

• Manufacturer Part Number: PAC-SYSTEMCLK5520
• Description: Development Software ispCLK5520 Design Sys
• Manufacturer: Lattice

Specifications of PAC-SYSTEMCLK5520

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 19 shows how ispClock5500 reference input should be configured for accepting these standards.
The major difference between the differential and single-ended forms of these logic standards is that in the differen-
tial cases, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are
engaged and set to 50Ω.
Figure 19. Differential HSTL/SSTL Receiver Configuration
LVDS/Differential LVPECL
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50Ω. The REFVTT pin, however, should be left unconnected. This creates a floating 100Ω dif-
ferential termination resistance across the input terminals. The LVDS termination configuration is shown in
Figure 20.
Figure 20. LVDS Input Receiver Configuration
Driver
LVDS
VTT
+Signal In
-Signal In
REFVTT
REFA+
REFA-
-Signal In
+Signal In
ispClock5500
50
CLOSED
No Connect
REFVTT
50
REFA+
REFA-
23
CLOSED
ispClock5500
50
Differential
Receiver
CLOSED
ispClock5500 Family Data Sheet
50
CLOSED
Differential
Receiver