PAC-SYSTEMCLK5520 Lattice, PAC-SYSTEMCLK5520 Datasheet - Page 22

• Manufacturer Part Number: PAC-SYSTEMCLK5520
• Description: Development Software ispCLK5520 Design Sys
• Manufacturer: Lattice

Specifications of PAC-SYSTEMCLK5520

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 17. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
V
shows an appropriate configuration. Refer to the “Recommended Operating Conditions - Supported Logic Stan-
dards” table in this data sheet for suitable values of V
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 18. SSTL2, SSTL3, HSTL Receiver Configuration
TT
termination supply. The positive input’s terminating resistor should be engaged and set to 50Ω. Figure 18
VTT
Signal In
VREF IN
Signal In
No Connect
No Connect
REFVTT
REFA+
REFA-
REFVTT
REFA+
REFA-
ispClock5500
50
ispClock5500
R
CLOSED
T
OPEN
REF
22
and V
OPEN
ref
value, and the REFVTT terminal should be tied to a
TT.
Differential
Receiver
ispClock5500 Family Data Sheet
Single-ended
Receiver