PAC-SYSTEMCLK5520 Lattice, PAC-SYSTEMCLK5520 Datasheet - Page 21

• Manufacturer Part Number: PAC-SYSTEMCLK5520
• Description: Development Software ispCLK5520 Design Sys
• Manufacturer: Lattice

Specifications of PAC-SYSTEMCLK5520

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Clock reference inputs may be configured to interface to signals from the following logic families with little or no
external support circuitry:
Each input also features internal programmable termination resistors, as shown in Figure 16.
Figure 16. ispClock5500 Clock Reference Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left floating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 17 shows the proper
configuration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate configuration setting for this particular standard.
• LVTTL (3.3V)
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
• LVDS
• LVPECL (differential, 3.3V)
REFVTT
REFA+
REFA-
ispClock5500
R
T
R
T
Single-ended
Differential
21
Receiver
Receiver
ispClock5500 Family Data Sheet
To Internal
Logic