PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 91

• Manufacturer Part Number: PN5120A0HN/C2,551
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C2,551

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
14. Interrupt request system
PN512
Product data sheet
COMPANY PUBLIC
14.1 Interrupt sources overview
If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation
The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
Table 156
for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set
by the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see
page
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
Table 156. Interrupt sources
LoAlert
Interrupt flag
TimerIRq
TxIRq
CRCIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
ErrIRq
97).
=
4:
shows the available interrupt bits, the corresponding source and the condition
FIFOLength
Interrupt source
timer unit
transmitter
CRC coprocessor
receiver
ComIrqReg register
FIFO buffer
FIFO buffer
contactless UART
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
≤
WaterLevel
111336
Trigger action
the timer counts from 1 to 0
a transmitted data stream ends
all data from the FIFO buffer has been processed
a received data stream ends
command execution finishes
the FIFO buffer is almost full
an error is detected
the FIFO buffer is almost empty
Transmission module
© NXP B.V. 2011. All rights reserved.
PN512
Table 157 on
91 of 125
(4)