PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 71

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PN5120A0HN/C2,551

Manufacturer Part Number
PN5120A0HN/C2,551
Description
IC TRANSMISSION MOD 40-HVQFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PN5120A0HN/C2,551

Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
40-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PN5120A0HN/C2,551
Manufacturer:
COPAL
Quantity:
12
NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
10.4 I
The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is
set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for
future use, and bits 5 to 0 define the address; see
Table 150. Address byte 0 register; address MOSI
An I
interface to the host. The I
NXP Semiconductors’ I
interface can only act in Slave mode. Therefore the PN512 does not implement clock
generation or access arbitration.
The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast
mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
PN512 has a 3-state output stage to perform the wired-AND function. Data on the I
can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast
mode or up to 3.4 Mbit/s in High-speed mode.
If the I
as defined in the I
See
7 (MSB)
1 = read
0 = write
2
Fig 16. I
C Bus Interface
2
Table 170 on page 108
C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus
2
C-bus interface is selected, spike suppression is activated on lines SCL and SDA
2
C-bus interface
6
reserved
All information provided in this document is subject to legal disclaimers.
MICROCONTROLLER
2
C-bus interface specification.
Rev. 3.6 — 10 March 2011
5
address
2
C-bus interface specification, rev. 2.1, January 2000. The
2
C-bus interface is implemented according to
for timing requirements.
111336
4
NETWORK
PULL-UP
CONFIGURATION
WIRING
3
NETWORK
PULL-UP
Table
150.
2
SDA
SCL
I2C
EA
ADR_[5:0]
PN512
Transmission module
1
001aan222
© NXP B.V. 2011. All rights reserved.
PN512
0 (LSB)
71 of 125
2
C-bus

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