PN5120A0HN/C1,518 NXP Semiconductors, PN5120A0HN/C1,518 Datasheet - Page 35

• Manufacturer Part Number: PN5120A0HN/C1,518
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,518

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.2.4 RxModeReg
Defines the data rate and framing during reception.
Table 52.
Table 53.
Bit
7
6 to 4
3
2
1 to 0
Access
Rights
RxCRCEn
Symbol
RxCRCEn
RxSpeed
RxNoErr
RxMultiple
RxFraming
RxModeReg register (address 13h); reset value: 00h, 00000000b
Description of RxModeReg bits
r/w
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
dy
Description
Set to logic 1, this bit enables the CRC calculation during reception.
Note: This bit shall only be set to logic 0 at 106 kbit.
Defines the bit rate while data transmission.
The PN512’s analog part handles only transfer speeds up to 424 kbit
internally, the digital UART handles the higher transfer speeds as well.
Value
000
001
010
011
100
101
110
111
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
If set to logic 1 a not valid received data stream (less than 4 bits
received) will be ignored. The receiver will remain active.
For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non
valid datastream.
Set to logic 0, the receiver is deactivated after receiving a data frame.
Set to logic 1, it is possible to receive more than one data frame. Having
set this bit, the receive and transceive commands will not terminate
automatically. In this case the multiple receiving can only be deactivated
by writing any command (except the Receive command) to the
CommandReg register or by clearing the bit by the host controller.
If set to logic 1, at the end of a received data stream an error byte is
added to the FIFO. The error byte is a copy of the ErrorReg register.
Defines the expected framing for data reception.
Value
00
01
10
11
6
RxSpeed
111336
dy
5
Description
106 kbit
212 kbit
424 kbit
848 kbit
1696 kbit
3392 kbit
Reserved
Reserved
Description
ISO/IEC 14443A/MIFARE and Passive Communication
mode 106 kbit
Active Communication mode
FeliCa and Passive Communication mode 212 and 424 kbit
ISO/IEC 14443B
dy
4
RxNoErr
r/w
3
RxMultiple
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
dy
1
RxFraming
PN512
35 of 125
dy
0