PN5120A0HN/C1,518 NXP Semiconductors, PN5120A0HN/C1,518 Datasheet - Page 17

• Manufacturer Part Number: PN5120A0HN/C1,518
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,518

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
9. PN512 register SET
PN512
Product data sheet
COMPANY PUBLIC
8.4.6 FeliCa Card operation mode
9.1 PN512 registers overview
Table 13.
Table 14.
Communication
direction
reader/writer →
PN512
PN512 → reader/
writer
Addr
(hex)
Page 0: Command and Status
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page 1: Command
0
1
2
3
4
5
Register Name
PageReg
CommandReg
ComlEnReg
DivlEnReg
ComIrqReg
DivIrqReg
ErrorReg
Status1Reg
Status2Reg
FIFODataReg
FIFOLevelReg
WaterLevelReg
ControlReg
BitFramingReg
CollReg
RFU
PageReg
ModeReg
TxModeReg
RxModeReg
TxControlReg
TxAutoReg
FeliCa Card operation mode
PN512 registers overview
All information provided in this document is subject to legal disclaimers.
Transfer speed
Modulation on reader side
bit coding
Bitlength
Load modulation on PN512
side
bit coding
Rev. 3.6 — 10 March 2011
Function
Selects the register page
Starts and stops command execution
Controls bits to enable and disable the passing of Interrupt Requests
Controls bits to enable and disable the passing of Interrupt Requests
Contains Interrupt Request bits
Contains Interrupt Request bits
Error bits showing the error status of the last command executed
Contains status bits for communication
Contains status bits of the receiver and transmitter
In- and output of 64 byte FIFO-buffer
Indicates the number of bytes stored in the FIFO
Defines the level for FIFO under- and overflow warning
Contains miscellaneous Control Registers
Adjustments for bit oriented frames
Bit position of the first bit collision detected on the RF-interface
Reserved for future use
Selects the register page
Defines general modes for transmitting and receiving
Defines the data rate and framing during transmission
Defines the data rate and framing during receiving
Controls the logical behavior of the antenna driver pins TX1 and TX2
Controls the setting of the antenna drivers
111336
FeliCa
212 kbit/s
8-30 % ASK
Manchester Coding
(64/13.56) μs
> 12 % ASK load
modulation
Manchester coding
Transmission module
FeliCa Higher
transfer speeds
424 kbit/s
8-30 % ASK
Manchester Coding
(32/13.56) μs
> 12 % ASK load
modulation
Manchester coding
© NXP B.V. 2011. All rights reserved.
PN512
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