CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 9

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

DS773DB1
3.2
(on-board osc.)
24 MHz
AIN2A
AIN1B
AIN1A
AIN2B
Analog In to S/PDIF or PSIA Out
The CS42L55 analog front-end performance can be tested by selecting the “SPDIF In to Analog Out --
Analog In to S/PDIF Out” or “PSIA In to Analog Out -- Analog In to PSIA Out” quick setup file provided
with the software package. Note: The Control Port Compensation script for the associated VA supply
must also be selected. The script configures the digital clock and data signal routing on the board as shown
in
is populated in Y1.
A S/PDIF input must be provided as the S/PDIF Tx (CS8406) uses the RMCK signal from the S/PDIF Rx
(CS8416) for synchronization in this configuration.
Figure
3. The quick setup scripts provided in the software assume that a 24.000 MHz on-board oscillator
12 MHz MCLK
AIN1B
AIN1A
AIN2A
AIN2B
CS42L55
ADC.SDOUT
Divider
(Slave)
PLL &
Figure 3. Analog In to S/PDIF or PSIA Out
SCLK
LRCK
FPGA
(CS8421)
Rx SRC
(Slave)
RX.SCLK
RX.LRCK
RX.SDIN
PSIA Rx (J40)
TX.LRCK
TX.SCLK
S/PDIF Tx
(CS8406)
TX.SDIN
(Master)
CDB42L55
S/PDIF
OUT
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