EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 50

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
•
•
Software Master Mode
The ADuC841/ADuC842/ADuC843 can be used as I
devices by configuring the I
writing software to output the data bit by bit. This is referred to
as a software master. Master mode is enabled by setting the I2CM
bit in the I2CCON register.
To transmit data on the SDATA line, MDE must be set to enable
the output driver on the SDATA pin. If MDE is set, the SDATA
pin is pulled high or low depending on whether the MDO bit is
set or cleared. MCO controls the SCLOCK pin and is always
configured as an output in master mode. In master mode, the
SCLOCK pin is pulled high or low depending on the whether
MCO is set or cleared.
To receive data, MDE must be cleared to disable the output
driver on SDATA. Software must provide the clocks by toggling
the MCO bit and reading the SDATA pin via the MDI bit. If
MDE is cleared, MDI can be used to read the SDATA pin. The
value of the SDATA pin is latched into MDI on a rising edge of
SCLOCK. MDI is set if the SDATA pin was high on the last
rising edge of SCLOCK. MDI is clear if the SDATA pin was low
on the last rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to
generate the start condition, slave address, acknowledge bits,
data bytes, and stop conditions. These functions are described
in Application Note uC001.
Hardware Slave Mode
After reset, the ADuC841/ADuC842/ADuC843 default to
hardware slave mode. The I
the SPE bit in SPICON (this is not necessary if the MSPI bit is
set). Slave mode is enabled by clearing the I2CM bit in I2CCON.
The parts have a full hardware slave. In slave mode, the I
address is stored in the I2CADD register. Data received or to be
transmitted is stored in the I2CDAT register.
An I
without a stop bit in between. This allows a master to
change direction of transfer without giving up the bus.
Note that the repeated start is detected only when a slave
has previously been configured as a receiver.
On-chip filtering rejects <50 ns spikes on the SDATA and
the SCLOCK lines to preserve data integrity.
2
C slave can respond to repeated start conditions
MASTER
I
2
C
Figure 55. Typical I
2
2
DV
C interface is enabled by clearing
C peripheral in master mode and
DD
2
C System
SLAVE 1
SLAVE 2
I
I
2
2
C
C
2
C master
2
C
Rev. 0 | Page 50 of 88
Once enabled in I
start condition. If the part detects a valid start condition, fol-
lowed by a valid address, followed by the R/ W bit, the I2CI
interrupt bit is automatically set by hardware. The I
generates a core interrupt only if the user has pre-configured
the I
global interrupt bit, EA , in the IE SFR. i.e.,
;Enabling I2C Interrupts for the ADuC842
MOV IEIP2,#01h
SETB EA
An autoclear of the I2CI bit is implemented on the parts so that
this bit is cleared automatically on a read or write access to the
I2CDAT SFR.
MOV I2CDAT, A
MOV A, I2CDAT
If for any reason the user tries to clear the interrupt more than
once, i.e., access the data SFR more than once per interrupt, then
the I
reset using the I2CRS bit.
The user can choose to poll the I2CI bit or to enable the inter-
rupt. In the case of the interrupt, the PC counter vectors to
003BH at the end of each complete byte. For the first byte, when
the user gets to the I2CI ISR, the 7-bit address and the R/ W bit
appear in the I2CDAT SFR.
The I2CTX bit contains the R/ W bit sent from the master. If
I2CTX is set, the master is ready to receive a byte. Therefore the
slave will transmit data by writing to the I2CDAT register. If
I2CTX is cleared, the master is ready to transmit a byte. There-
fore the slave will receive a serial byte. Software can interrogate
the state of I2CTX to determine whether it should write to or
read from I2CDAT.
Once the part has received a valid address, hardware holds
SCLOCK low until the I2CI bit is cleared by software. This
allows the master to wait for the slave to be ready before
transmitting the clocks for the next byte.
The I2CI interrupt bit is set every time a complete data byte is
received or transmitted, provided it is followed by a valid ACK.
If the byte is followed by a NACK, an interrupt is not generated.
The part continues to issue interrupts for each complete data
byte transferred until a stop condition is received or the inter-
face is reset.
When a stop condition is received, the interface resets to a state
in which it is waiting to be addressed (idle). Similarly, if the
interface receives a NACK at the end of a sequence, it also
returns to the default idle state. The I2CRS bit can be used to
reset the I
back to the default idle state.
2
2
C interrupt enable bit in the IEIP2 SFR as well as the
C controller will halt. The interface will then have to be
2
C interface. This bit can be used to force the interface
2
C slave mode, the slave controller waits for a
; enable I2C interrupt
; I2CI auto-cleared
; I2CI auto-cleared
2
C peripheral