EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 30

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC841/ADuC842/ADuC843
The DMA logic operates from the ADC clock and uses pipelin-
ing to perform the ADC conversions and to access the external
memory at the same time. The time it takes to perform one ADC
conversion is called a DMA cycle. The actions performed by the
logic during a typical DMA cycle are shown in Figure 36.
Figure 36 shows that during one DMA cycle, the following
actions are performed by the DMA logic:
1.
2.
3.
For the previous example, the complete flow of events is shown
in Figure 36. Because the DMA logic uses pipelining, it takes
three cycles before the first correct result is written out.
Micro Operation during ADC DMA Mode
During ADC DMA mode, the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, note that MCU core accesses to
Ports 0 and 2 (which of course are being used by the DMA con-
troller) are gated off during the ADC DMA mode of operation.
This means that even though the instruction that accesses the
external Ports 0 or 2 appears to execute, no data is seen at these
external ports as a result. Note that during DMA to the inter-
nally contained XRAM, Ports 0 and 2 are available for use.
The only case in which the MCU can access XRAM during
DMA is when the internal XRAM is enabled and the section of
RAM to which the DMA ADC results are being written to lies
in an external XRAM. Then the MCU can access the internal
XRAM only. This is also the case for use of the extended stack
pointer.
The MicroConverter core can be configured with an interrupt
to be triggered by the DMA controller when it has finished
filling the requested block of RAM with ADC results, allowing
the service routine for this interrupt to postprocess data without
any real-time timing constraints.
An ADC conversion is performed on the channel whose ID
was read during the previous cycle.
The 12-bit result and the channel ID of the conversion
performed in the previous cycle is written to the external
memory.
The ID of the next channel to be converted is read from
external memory.
CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE
PREVIOUS DMA CYCLE
CONVERTED DURING
WRITE ADC RESULT
Figure 36. DMA Cycle
DMA CYCLE
TO BE CONVERTED DURING
READ CHANNEL ID
NEXT DMA CYCLE
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ADC Offset and Gain Calibration Coefficients
The ADuC841/ADuC842/ADuC843 have two ADC calibration
coefficients, one for offset calibration and one for gain calibra-
tion. Both the offset and gain calibration coefficients are 14-bit
words, and are each stored in two registers located in the special
function register (SFR) area. The offset calibration coefficient is
divided into ADCOFSH (six bits) and ADCOFSL (8 bits), and
the gain calibration coefficient is divided into ADCGAINH
(6 bits) and ADCGAINL (8 bits).
The offset calibration coefficient compensates for dc offset
errors in both the ADC and the input signal. Increasing the
offset coefficient compensates for positive offset, and effectively
pushes the ADC transfer function down. Decreasing the offset
coefficient compensates for negative offset, and effectively
pushes the ADC transfer function up. The maximum offset that
can be compensated is typically ±5% of V
typically ±125 mV with a 2.5 V reference.
Similarly, the gain calibration coefficient compensates for dc
gain errors in both the ADC and the input signal. Increasing the
gain coefficient compensates for a smaller analog input signal
range and scales the ADC transfer function up, effectively
increasing the slope of the transfer function. Decreasing the
gain coefficient compensates for a larger analog input signal
range and scales the ADC transfer function down, effectively
decreasing the slope of the transfer function. The maximum
analog input signal range for which the gain coefficient can
compensate is 1.025
0.975
voltage.
CALIBRATING THE ADC
Two hardware calibration modes are provided, which can be
easily initiated by user software. The ADCCON3 SFR is used to
calibrate the ADC. Bit 1 (typical) and CS3 to CS0 (ADCCON2) set
up the calibration modes.
Device calibration can be initiated to compensate for significant
changes in operating condition frequency, analog input range,
reference voltage, and supply voltages. In this calibration mode,
offset calibration uses internal AGND selected via ADCCON2
register Bits CS3 to CS0 (1011), and gain calibration uses inter-
nal V
should be executed first, followed by gain calibration. System
calibration can be initiated to compensate for both internal and
external system errors. To perform system calibration by using
an external reference, tie the system ground and reference to
any two of the six selectable inputs. Enable external reference
mode (ADCCON1.6). Select the channel connected to AGND
via Bits CS3 to CS0 and perform system offset calibration. Select
the channel connected to V
system gain calibration.
REF
×
V
selected by Bits CS3 to CS0 (1100). Offset calibration
REF
, which equates to typically ±2.5% of the reference
×
V
REF
, and the minimum input range is
REF
via Bits CS3 to CS0 and perform
REF
, which equates to