AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 7

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD)
Table 8.
Parameter
DIFFERENTIAL OPERATION
SINGLE-ENDED OPERATION
REFERENCE MONITORS
Table 9.
Parameter
REFERENCE MONITORS
1
f
REF
Frequency Range
Minimum Input Slew Rate
Common-Mode Input Voltage
Differential Input Voltage Sensitivity
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
Frequency Range (CMOS)
Minimum Input Slew Rate
Input Voltage High (V
Input Voltage Low (V
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
Reference Monitor
Validation Timer
Redetect Timer
is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
Sinusoidal Input
LVPECL Input
LVDS Input
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Loss of Reference Detection
Frequency Out-of Range Limits
Time
IL
IH
)
)
Min
9.54 × 10
0.001
0.001
−7
Min
10
1
1
40
620
620
1
40
1.5
1.5
0.9
1.2
1.9
Typ
Rev. A | Page 7 of 112
Max
1.2
0.1
65.535
65.535
Typ
2
±65
25
3
45
3
Unit
sec
Δf/f
sec
sec
REF
Max
750
750 × 10
750 × 10
250 ×10
0.27
0.5
1.0
Test Conditions/Comments
Calculated using the nominal phase detector period
(NPDP = R/f
Programmable (lower bound subject to quality of SYSCLK)
Programmable in 1 ms increments
Programmable in 1 ms increments
6
6
6
Unit
MHz
Hz
Hz
V/μs
V
mV
kΩ
pF
ps
ps
Hz
V/μs
V
V
V
V
V
V
kΩ
pF
ns
ns
REF
)
1
Test Conditions/Comments
Minimum limit imposed for jitter
performance
Internally generated
Minimum differential voltage across
pins required to ensure switching
between logic levels; the
instantaneous voltage on either pin
must not exceed the supply rails
Minimum limit imposed for jitter
performance
AD9548