AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 60

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
REGISTER MAP
Table 35.
Addr
0000
0001
0002
0003
0004
0005
0100
0101
0102
0103
0104
0105
0106
0107
0108
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
020A
020B
020C
020D
020E
020F
0000
Opt
E
Dup
E
R
R
E
A, E
S
S
S
C
C
C
C
C
C
S
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
Name
SPI control
I2C control
Reserved
Reserved
Readback
I/O update
Nom SYSCLK
period
System clock
stability
M0
M1
M2
M3
M4
M5
M6
M7
IRQ pin
output mode
IRQ mask
D7
Unidirec-
tional
Unused
Unused
Silicon revision number
Device ID
Unused
Unused
External
loop filter
enable
N-divider [7:0]
Unused
Nominal system clock period (femtoseconds) [15:0]
[1 ns @ 1 ppm accuracy]
Unused
System clock stability period (milliseconds) [15:0]
Unused
M0 in/out
M1 in/out
M2 in/out
M3 in/out
M4 in/out
M5 in/out
M6 in/out
M7 in/out
Unused
Unused
Unused
Switching
Unused
Ref AA
new profile
Ref BB
new profile
Ref CC
new profile
D6
LSB first/
Inc Addr
Charge
pump
mode
(auto/
man)
M-divider
reset
M0 function [6:0]
M1 function [6:0]
M2 function [6:0]
M3 function [6:0]
M4 function [6:0]
M5 function [6:0]
M6 function [6:0]
M7 function [6:0]
Closed
Ref AA
validated
Ref BB
validated
Ref CC
validated
D5
Soft reset
Soft reset
Charge pump current [2:0]
M-divider [1:0]
SYSCLK
unlocked
Freerun
Ref AA
fault
cleared
Ref BB
fault
cleared
Ref CC
fault
cleared
Rev. A | Page 60 of 112
Serial port control and part identification
D4
Long
instruction
Unused
Nominal system clock period [20:16]
SYSCLK
locked
Holdover
History
updated
Ref AA
fault
Ref BB
fault
Ref CC
fault
General configuration
System clock
Distribution
sync
Frequency
unclamped
2×
frequency
multiplier
enable
D3
Unused
System clock stability period (milliseconds) [19:16]
Unused
Freq
unlocked
Ref A
new
profile
Ref B
new
profile
Ref C
new
profile
D2
Lock
detect
timer
disable
PLL enable
Unused
Watchdog
timer
Freq
locked
Frequency
clamped
Ref A
validated
Ref B
validated
Ref C
validated
D1
SYSCLK reference select
[1:0]
IRQ pin output mode
[1:0]
SYSCLK Cal
complete
EEPROM
fault
Phase
unlocked
Phase slew
unlimited
Ref A
fault
cleared
Ref B
fault
cleared
Ref C
fault
cleared
Lock detect divider [1:0]
D0
Read
buffer
register
I/O update
SYSCLK Cal
started
EEPROM
complete
Phase
locked
Phase slew
limited
Ref A
fault
Ref B
fault
Ref C
fault
Def
10
00
C5
48
00
00
18
28
45
40
42
0F
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00