AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 5

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
1
2
3
LOGIC INPUTS (M7 TO M0, RESET, TDI, TCLK, TMS)
Table 4.
Parameter
LOGIC INPUTS (M7 to M0, RESET, TDI, TCLK, TMS)
LOGIC OUTPUTS (M7 TO M0, IRQ, TDO)
Table 5.
Parameter
LOGIC OUTPUTS (M7 to M0, IRQ, TDO)
SYSTEM CLOCK INPUTS (SYSCLKP/SYSCLKN)
Table 6.
Parameter
SYSTEM CLOCK PLL BYPASSED
f
f
f
SYSCLK
S
DDS
Incremental Power Dissipation
Input High Voltage (V
Input Low Voltage (V
Input Current (I
Input Capacitance (C
Output High Voltage (V
Output Low Voltage (V
IRQ Leakage Current
Input Frequency Range
Minimum Input Slew Rate
Duty Cycle
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
is the sample rate of the output DAC.
is the output frequency of the DDS.
SYSCLK PLL Off
Input Reference On
Output Distribution Driver On
Active Low Output Mode
Active High Output Mode
is the frequency at the SYSCLKP and SYSCLKN pins.
Differential
Single-Ended
LVDS
LVPECL
CMOS
INH
, I
INL
IL
IN
)
IH
)
)
OL
)
OH
)
)
Min
Min
500
1000
40
100
Min
2.1
Min
2.7
Typ
−105
7
13
70
75
65
Typ
1.2
2
2.5
Rev. A | Page 5 of 112
Max
Typ
±80
3
Typ
Max
1000
60
Unit
mW
mW
mW
mW
mW
mW
Max
0.8
±200
Max
0.4
1
1
Test Conditions/Comments
Conditions = typical configuration; table values show the
change in power due to the indicated operation.
f
A single 3.3 V CMOS output with a 10 pF load.
SYSCLK
Unit
MHz
V/μs
%
V
mV p-p
pF
kΩ
= 1 GHz
Unit
V
V
μA
pF
Unit
V
V
μA
μA
1
; high frequency direct input mode.
Test Conditions/Comments
Minimum limit imposed for jitter
performance
Internally generated
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Single-ended, each pin
Test Conditions/Comments
Test Conditions/Comments
I
I
Open-drain mode
V
V
OH
OL
OH
OL
= 1 mA
= 1 mA
=-0 V
= 3.3 V
AD9548