AD9957/PCBZ Analog Devices Inc, AD9957/PCBZ Datasheet - Page 18
![D/A Converter Evaluation Board](/photos/9/5/90540/ad9957_pcbz_sml.jpg)
AD9957/PCBZ
Manufacturer Part Number
AD9957/PCBZ
Description
D/A Converter Evaluation Board
Manufacturer
Analog Devices Inc
Series
AgileRF™r
Datasheet
1.AD9957BSVZ-REEL.pdf
(64 pages)
Specifications of AD9957/PCBZ
Silicon Manufacturer
Analog Devices
Application Sub Type
Direct Digital Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9957
Kit Contents
Board
Main Purpose
Timing: DDS Modulators
Embedded
No
Utilized Ic / Part
AD9957
Primary Attributes
14-Bit DAC, 32-Bit Tuning Word Width
Secondary Attributes
1GHz, Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9957/PCBZ
Manufacturer:
LT
Quantity:
962
AD9957
BLACKFIN INTERFACE (BFI) MODE
A subset of the QDUC mode is the Blackfin interface (BFI)
mode, shown in Figure 27; grayed items are inactive. In this
mode, a separate I and Q serial bit stream is applied to the
baseband data port instead of parallel data-words. The two
serial inputs provide for 16-bit I- and Q-words (unlike the
18-bit words in normal QDUC mode). The serial bit streams
are delivered to the Blackfin interface. The Blackfin interface
converts the 16-bit serial data into 16-bit parallel data to
propagate down the signal processing chain.
TxENABLE
PDCLK
I/Q IN
FTW
PW
2
TIMING AND CONTROL
PROGRAMMING
PARALLEL DATA
REGISTERS
3
18
16
16
18
QS
Q
IS
I
SERIAL I/O
PORT
Figure 27. Quadrature Modulation Mode, Blackfin Interface
INTERNAL CLOCK TIMING AND CONTROL
I Q
RAM
Rev. B | Page 18 of 64
IS QS
OSK
AD9957
cos (ωt+θ)
θ
ω
sin (ωt+θ)
CLOCK
CONTROL
DDS
POWER
DOWN
The Blackfin interface includes an additional pair of half-band
filters in both I and Q signal paths (not shown explicitly in the
diagram). The two half-band filters increase the interpolation
of the baseband data by a factor of four, relative to the normal
QDUC mode.
The synchronization of the serial data occurs through the
PDCLK signal. In BFI mode, the PDCLK signal is effectively
the bit clock for the serial data.
Note that the system clock is limited to 750 MHz in BFI mode.
2
2
SYSCLK
DAC GAIN
PLL
÷2
8
OUTPUT
FACTOR
SCALE
8-BIT
AUX
DAC
14-BIT
DAC
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
XTAL_SEL