AD9276-65EBZ Analog Devices Inc, AD9276-65EBZ Datasheet - Page 39

• Manufacturer Part Number: AD9276-65EBZ
• Description: 65MSPS ADC Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9276-65EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9276
• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: *
• Power (typ) @ Conditions: 195mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9276
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL PORT INTERFACE (SPI)
The AD9276 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. The SPI
offers the user added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the Analog Devices, Inc., AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Three pins define the serial port interface, or SPI: SCLK, SDIO,
and CSB (see Table 16). The SCLK (serial clock) pin is used to
synchronize the read and write data presented to the device. The
SDIO (serial data input/output) pin is a dual-purpose pin that
allows data to be sent to and read from the internal memory map
registers of the device. The CSB (chip select bar) pin is an active
low control that enables or disables the read and write cycles.
Table 17. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
SCLK
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
SDIO
CSB
DON’T
CARE
DON’T
CARE
t
S
R/W
Timing (ns min)
5
2
40
5
2
16
16
10
10
t
DS
W1
W0
t
DH
t
A12
HIGH
t
LOW
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 76)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 76)
A11
A10
Figure 76. Serial Timing Details
A9
Rev. 0 | Page 39 of 48
t
CLK
A8
A7
Table 16. Serial Port Pins
Pin
SCLK
SDIO
CSB
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its defini-
tions can be found in Figure 76 and Table 17.
Function
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Serial data input/output. Dual-purpose pin that
typically serves as an input or an output, depending
on the instruction sent and the relative position in
the timing frame.
Chip select bar (active low). This control gates the
read and write cycles.
D5
D4
D3
D2
D1
D0
t
H
AD9276
DON’T
CARE
DON’T
CARE