AD9276-65EBZ Analog Devices Inc, AD9276-65EBZ Datasheet
AD9276-65EBZ
Specifications of AD9276-65EBZ
Related parts for AD9276-65EBZ
AD9276-65EBZ Summary of contents
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... ADC LVDS AAF SERIAL REFERENCE PORT INTERFACE Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9276 DOUTA+ TO DOUTH+ DOUTA– TO DOUTH– FCO+ DATA FCO– RATE DCO+ MULTIPLIER DCO– www.analog.com ©2009 Analog Devices, Inc. All rights reserved. ...
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... AD9276 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 8 ADC Timing Diagrams ............................................................... 9 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 14 TGC Mode ................................................................................... 14 CW Doppler Mode ...
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... GENERAL DESCRIPTION The AD9276 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti- aliasing filter (AAF); a 12-bit, 10 MSPS to 80 MSPS analog-to- digital converter (ADC); and an I/Q demodulator with programmable phase rotation ...
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... AD9276 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF cutoff = f Mode MSPS, Mode SAMPLE otherwise noted. Table 1. 1 Parameter LNA CHARACTERISTICS Gain Input Voltage Range (Single-Ended) Input Common Mode (LI-x, LG-x) ...
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... AD9276 Unit LSB dBFS dBFS dBc dBc dBc dBc dBc dB dB Degrees dB/V ns MΩ ...
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... AD9276 1 Parameter Input-Referred Noise Voltage Noise Figure Input-Referred Dynamic Range Output-Referred SNR Two-Tone Intermodulation (IMD3) Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching POWER SUPPLY Mode I/Mode II/Mode III AVDD1 AVDD2 DRVDD I AVDD1 I AVDD2 I DRVDD Total Power Dissipation (Including Output Drivers) ...
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... MHz, full temperature, unless otherwise noted. Typ Max CMOS/LVDS/LVPECL 1.2 20 1.5 CMOS/LVDS/LVPECL 1.2 20 1.5 3.6 0.3 30 0.5 3.6 0.3 70 0.5 DRVDD + 0.3 0 1.79 0.05 LVDS 454 1.375 Offset binary LVDS 250 1.30 Offset binary 0.05 AD9276 Unit mV p-p V kΩ p-p V kΩ kΩ kΩ kΩ ...
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... AD9276 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 3. 1 Parameter 2 CLOCK Clock Rate 40 MSPS (Mode I) 65 MSPS (Mode II) 80 MSPS (Mode III) Clock Pulse Width High ( Clock Pulse Width Low ( OUTPUT PARAMETERS 2, 3 Propagation Delay (t ...
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... N – – 8 Figure 2. 12-Bit Data Serial Stream (Default FRAME t DATA LSB – – – – – – – 8 Figure 3. 12-Bit Data Serial Stream, LSB First Rev Page AD9276 MSB D10 N – – – – – – – D10 LSB N – – – ...
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... AD9276 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD1 to GND AVDD2 to GND DRVDD to GND GND to GND AVDD2 to AVDD1 AVDD1 to DRVDD AVDD2 to DRVDD Digital Outputs (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) to GND CLK+, CLK−, SDIO to GND LI-x, LO-x, LOSW-x to GND CWI− ...
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... LNA Analog Switched Output for Channel G. LNA Analog Input for Channel G. LNA Ground for Channel G. LNA Analog Inverted Output for Channel H. LNA Analog Switched Output for Channel H. LNA Analog Input for Channel H. LNA Ground for Channel H. Rev Page AD9276 LI-D 75 LG-D 74 AVDD2 73 AVDD1 ...
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... AD9276 Pin No. Name 23 CLK− 24 CLK+ 26, 47 DRVDD 27 DOUTH− 28 DOUTH+ 29 DOUTG− 30 DOUTG+ 31 DOUTF− 32 DOUTF+ 33 DOUTE− 34 DOUTE+ 35 DCO− 36 DCO+ 37 FCO− 38 FCO+ 39 DOUTD− 40 DOUTD+ 41 DOUTC− 42 DOUTC+ 43 DOUTB− 44 DOUTB+ 45 DOUTA− 46 DOUTA+ 48 STBY 49 PDWN 51 SCLK ...
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... LOSW-E Description External Resistor to Set the Internal ADC Core Bias Current. Voltage Reference Input/Output. CW Doppler I Output Complement. CW Doppler I Output True. CW Doppler Q Output Complement. CW Doppler Q Output True. LNA Analog Inverted Output for Channel E. LNA Analog Switched Output for Channel E. Rev Page AD9276 ...
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... AD9276 TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE MSPS MHz Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = f SAMPLE IN S HPF cutoff = LPF cutoff/20.7 (default). 2.0 1.5 1.0 –40°C 0.5 +25°C 0 +85°C –0.5 –1.0 –1.5 –2 ...
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... GAIN+ (V) SNR SINAD 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 GAIN+ (V) MODE III – 80MSPS MODE II – 65MSPS MODE I – 40MSPS FREQUENCY (MHz) /3 (Mode I and Mode II), f /4.5 (Mode III) SAMPLE SAMPLE AD9276 1.6 1.5 1.6 40 ...
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... AD9276 0 –10 –20 –30 –40 GAIN+ = 0.4V –50 –60 GAIN+ = 1.6V –70 GAIN+ = 1.0V –80 – INPUT FREQUENCY (MHz) Figure 17. Second-Order Harmonic Distortion vs. Frequency, AIN = −1.0 dBFS 0 –10 –20 –30 GAIN+ = 0.4V –40 –50 –60 –70 GAIN+ = 1.0V – INPUT FREQUENCY (MHz) Figure 18. Third-Order Harmonic Distortion vs. Frequency, AIN = − ...
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... BASEBAND FREQUENCY (Hz) Figure 27. Noise Figure vs. Baseband Frequency 130 135 140 145 150 155 160 165 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 BASEBAND FREQUENCY (Hz) Figure 28. Output-Referred SNR vs. Baseband Frequency AD9276 ...
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... AD9276 170 168 166 LNA GAIN = 15.6dB 164 LNA GAIN = 17.9dB 162 LNA GAIN = 21.3dB 160 158 156 154 FREQUENCY (MHz) Figure 29. Small-Signal Dynamic Range vs. RF Frequency Rev Page ...
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... Figure 34. Equivalent SDIO Input Circuit DRVDD DRVDD DRVDD V V DOUTx– DRGND Figure 35. Equivalent Digital Output Circuit AVDD1 SCLK, 350Ω PDWN, OR STBY 30kΩ Figure 36. Equivalent SCLK, PDWN, or STBY Input Circuit AVDD2 350Ω RESET Figure 37. Equivalent RESET Input Circuit AD9276 DOUTx+ ...
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... AD9276 AVDD1 AVDD1 70kΩ 350Ω CSB Figure 38. Equivalent CSB Input Circuit VREF 6kΩ Figure 39. Equivalent VREF Circuit 100Ω RBIAS Figure 40. Equivalent RBIAS Circuit AVDD2 GAIN+ Figure 41. Equivalent GAIN+ Input Circuit AVDD2 GAIN– Figure 42. Equivalent GAIN− Input Circuit CWx+, CWx– ...
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... THEORY OF OPERATION ULTRASOUND The primary application for the AD9276 is medical ultrasound. Figure 45 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution ...
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... AD9276 4LO– 4LO+ RESET R LO-x FB1 R LOSW-x FB2 T/R SWITCH C S LI-x LG TRANSDUCER CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides user- adjustable input impedance termination. The CW Doppler path includes an I/Q demodulator. The TGC path includes a differen- tial X-AMP® ...
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... Table 7 IN and C in terms because the dc levels at Pin LO-x FB Minimum R (Ω) R (Ω) C (pF 200 90 50 250 70 50 350 50 100 400 30 100 500 20 100 700 10 200 800 N/A 200 1000 N/A 200 1400 N/A AD9276 . FB 100M FB should (MHz ...
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... AD9276 LNA Noise The short-circuit noise voltage (input-referred noise important limit on system performance. The short-circuit noise voltage for the LNA is 0.75 nV/√ gain of 21.3 dB, including the VGA noise at a VGA postamp gain of 27 dB. These measure- ments, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 49 ...
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... RESET across the array ensures synchronized phase for all channels. Internal to the AD9276, the individual channel I and Q outputs are current summed. If multiple AD9276s are used, the I and Q outputs from each AD9276 can be current summed and converted to a voltage using an external transimpedance amplifier. ...
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... The maximum sum, when the AD8021 is used channels of the AD9276; that is, four AD9276s (4 × channels) can be summed in one AD8021. Rev Page AD8021 ...
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... Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the return- ing echo is derived. The primary application for the AD9276 I/Q demodulators is in analog beamforming circuits for ultrasound CW Doppler. ...
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... The function of the RESET pin is to phase align all the LO signals in multiple AD9276s. The 4LO divider of each AD9276 can be initiated in one of four possible states: 0°, 90°, 180°, and 270° relative to other AD9276s. The internally generated I/Q signals of each AD9276 LO are always at a 90° ...
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... MAX CHANNEL GAIN > 48dB Rev Page and Equation 4 is GAIN V (V) = (GAIN+) – (GAIN−) GAIN Gain (dB) = 28.5 dB/V × ICPT GAIN = 350 Ω). However, FB ADC FULL SCALE (2V p-p) ~10dB MARGIN 70dB ADC >11dB MARGIN ADC NOISE FLOOR (224µV rms) AD9276 (3) (4) ...
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... AD9276 Table 10. Sensitivity and Dynamic Range Trade-Offs LNA Gain Full-Scale Input Noise (V/V) (dB) Input (V p-p) (nV/√Hz) 6 15.6 0.733 0.98 8 17.9 0.550 0.86 12 21.3 0.367 0.75 1 LNA: output full scale = 4.4 V p-p differential. 2 Filter: loss ≈ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V. ...
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... Figure 61. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input. – POSTAMP Figure 60. Single-Ended GAIN+, GAIN− Pin Configuration Rev Page 100Ω 1.6V DC GAIN+ 0.01µF 50Ω GAIN– KELVIN 0.01µF CONNECTION AD9276 GAIN ...
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... AD9276 499Ω ±0.4V DC 100Ω AT 0.8V CM GAIN+ 0.01µF AD8138 100Ω GAIN– ±0.4V DC 0.01µF AT 0.8V CM 499Ω Figure 61. Differential GAIN+, GAIN− Pin Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The ...
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... This allows a wide range CLK– of clock input duty cycles without affecting the performance of the AD9276. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode ...
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... Figure 68. Ideal SNR vs. Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 69 and Figure 70, the power dissipated by the AD9276 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the LVDS output drivers ...
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... PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. By asserting the STBY pin high, the AD9276 is placed into a standby mode. In this state, the device typically dissipates 175 mW. During standby, the entire part is powered down except for the internal references ...
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... AD9276 600 EYE: ALL BITS 400 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 ULS: 2398/2398 0.5ns 1.0ns 1.5ns 100ps 200ps Figure 74 ...
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... Two output clocks are provided to assist in capturing data from ULS: 2396/2396 the AD9276. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9276 and must be captured on the rising and falling edges of DCO± ...
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... Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and that the AD9276 inverts the bit stream with relation to the ITU-T standard (see Table 14 for the initial values). ...
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... SERIAL PORT INTERFACE (SPI) The AD9276 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 16 constitute the physical interface between the user’s programming device and the serial port of the AD9276. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. ...
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... X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ” Similarly, “bit is cleared” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Rev Page AD9276 ...
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... AD9276 Table 18. AD9276 Memory Map Registers Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 0x00 chip_port_config 0 LSB first off (default) 0x01 chip_id 0x02 chip_grade X X Device Index and Transfer Registers 0x04 device_index_2 X X 0x05 device_index_1 X X 0xFF device_update X X Program Function Registers ...
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... Rev Page AD9276 Bit 0 Default Bit 1 (LSB) Value Comments X X 0x30 Antialiasing filter cutoff (global) ...
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... AD9276 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x19 user_patt1_lsb B7 B6 0x1A user_patt1_msb B15 B14 0x1B user_patt2_lsb B7 B6 0x1C user_patt2_msb B15 B14 0x21 serial_control LSB first off (default) 0x22 serial_ch_stat X X 0x2B flex_filter X Enable automatic low-pass tuning (self- clearing) 0x2C analog_input ...
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... AD9276. An exposed continuous copper plane on the PCB should mate to the AD9276 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB ...
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... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range 1 AD9276BSVZ −40°C to +85°C 1 AD9276-65EBZ 1 AD9276-80KITZ RoHS Compliant Part. 16.00 BSC SQ 14.00 BSC SQ 100 PIN 1 TOP VIEW (PINS DOWN ...
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... NOTES Rev Page AD9276 ...
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... AD9276 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08180-0-7/09(0) Rev Page ...