ADNS-9500 Avago Technologies US Inc., ADNS-9500 Datasheet - Page 31

• Manufacturer Part Number: ADNS-9500
• Description: Ultimate Gaming Laser Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-9500

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Frame_Capture
Access: R/W
Data Type: Bit Field.
USAGE: Used to capture the next available complete 1 frame of pixel values to be stored to SROM RAM. Writing to
SROM_Enable
Access: Write Only
Data Type: 8 Bit number.
USAGE: Write to this register to start either SROM download or SROM CRC test. See SROM Download section for details
Run_Downshift
Access: R/W
Data Type: 8 Bit number.
USAGE: This register set the Run to Rest 1 downshift time. Default value is 500ms. Use the formula below for calculation.
All the above values are calculated base on system clock, which expected to have 20% tolerance.
31
Bit
Field
Bit
Field
Bit
Field
this register will cause any firmware loaded in the SROM to be overwritten and stops navigation. A hardware
reset and SROM download are required to restore normal operation for motion reading. Refer to Frame Capture
section for use details.
SROM download procedure.
SROM CRC test can be performed to check for the successful of SROM downloading procedure. SROM CRC test
is only valid after SROM downloaded. Navigation is halted and the SPI port should not be used during this SROM
CRC test. Avago recommends reading the Motion register to determine the laser fault condition before perform-
ing the SROM CRC test.
SROM CRC test procedure is as below:
1. Write 0x15 to SROM_Enable register to start SROM CRC test.
2. Wait for at least 10ms.
3. Read the CRC value from Data_Lower and Data_Upper registers.
Run Downshift time (ms) = RD[7:0] x 10
Default = 50 x 10 = 500ms
7
FC
7
SE
7
RD
7
7
7
6
FC
6
SE
6
RD
6
6
6
Address: 0x12
Reset Value: 0x00
Address: 0x13
Reset Value: 0x00
Address: 0x14
Reset Value: 0x32
5
FC
5
SE
5
RD
5
5
5
4
FC
4
SE
4
RD
4
4
4
3
FC
3
SE
3
RD
3
3
3
2
FC
2
SE
2
RD
2
2
2
1
FC
1
SE
1
RD
1
1
1
0
FC
0
SE
0
RD
0
0
0