ACPL-W70L-560E Avago Technologies US Inc., ACPL-W70L-560E Datasheet - Page 11

• Manufacturer Part Number: ACPL-W70L-560E
• Description: Stretch Singles Pb-free TR VDE
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-W70L-560E

• Voltage - Isolation: 5000Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 10mA
• Data Rate: 15MBd
• Propagation Delay High - Low @ If: 23ns @ 6mA
• Current - Dc Forward (if): 10mA
• Input Type: DC
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount
• Package / Case: 6-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Powering Sequence
V
powering up the output connecting component.
Input Limiting Resistor
ACPL-W70L and ACPL-K73L are direct current driven (Fig-
ure 8), and thus eliminate the need for input power supply.
To limit the amount of current flowing through the LED, it
is recommended that a 530ohm resistor is connected in
series with anode of LED (i.e. Pin 1 for ACPL-W70L, Pin 1
and P4 for ACPL-K73L) at 5V input signal. At 3.3V input
signal, it is recommended to connect 250ohm resistor in
series with anode of LED. The recommended limiting re-
sistors is based on the assumption that the driver output
impedence is 50Ω (as shown in Figure 11).
Figure 11. Connection of peaking capacitor (C
limiting resistor (R
11
V
GND
DD
i
+
-
1
needs to achieve a minimum level of 4.5V before
R
50:
drv
=
llimit
C
R
peak
limit
) to improve speed performance
SHIELD
peak
) in parallel of the input
0.1μF
GND
V
V
DD2
O
2
Speed Improvement
A peaking capacitor can be placed across the input cur-
rent limit resistor (Figure 11) to achieve enhanced speed
performance. The value of the peaking cap is dependent
to the rise and fall time of the input signal and supply volt-
ages and LED input driving current (I
significant improvement of propagation delay and pulse
with distortion with added 100pF peak capacitor at driv-
ing current of 6mA and 5V power supply.
(i) V
(ii) V
Figure 12. Improvement of t
in parallel of input limiting resistor.
35
30
25
20
15
10
40
35
30
25
20
15
10
5
0
5
0
-40
DD2
-40
DD2
=5V, C
=3.3V, C
-20
peak
-20
peak
=100pF, R
|PWD|
t
=100pF, R
t
PLH
0
0
limit
p
t
t
and PWD with added 100pF peaking capacitor
PHL
limit
PHL
=530Ω
20
20
=250Ω
t
t
PHL
t
t
PLH
PHL
PLH
40
40
|PWD|
Without peaking cap
Without peaking cap
f
). Figure 12 shows
60
60
With peaking cap
With peaking cap
80
80
100
100