STM32F103ZGH6 STMicroelectronics, STM32F103ZGH6 Datasheet - Page 108

• Manufacturer Part Number: STM32F103ZGH6
• Description: MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103ZGH6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 21x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: STM32F101xG
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 112
• Number Of Timers: 15
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: STM32F103ZG
• Supply Current (max): 28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-11115

Electrical characteristics
Table 63.
1. Guaranteed by design, not tested in production.
2. Preliminary values.
Figure 59. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
108/120
INL
Offset
Gain
error
t
Update
rate
t
PSRR+
SETTLING
WAKEUP
Symbol
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
(2)
(2)
(2)
(2)
(1)
(2)
(2)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
V
Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
Power supply rejection ratio
(to V
measurement
DAC characteristics (continued)
REF+
DDA
/2)
) (static DC
Parameter
Buffered/Non-buffered DAC
12-bit
digital to
analog
converter
Min
Doc ID 16554 Rev 2
3
6.5
–67
Buffer(1)
Typ
±1
±4
±10
±3
±12
±0.5
4
1
10
–40
Max
DACx_OUT
LSB
LSB
mV
LSB
LSB
%
µs
MS/s C
µs
dB
Unit
C
R
Given for the DAC in 10-bit
configuration
Given for the DAC in 12-bit
configuration
Given for the DAC in 12-bit
configuration
Given for the DAC in 10-bit at V
= 3.6 V
Given for the DAC in 12-bit at V
= 3.6 V
Given for the DAC in 12bit
configuration
C
C
input code between lowest and
highest possible ones.
No R
LOAD
LOAD
LOAD
LOAD
LOAD
STM32F103xF, STM32F103xG
LOAD
 50 pF, R
 50 pF, R
 50 pF, R
, C
LOAD
Comments
ai17157
LOAD
LOAD
LOAD
= 50 pF
 5 k
 5 k
 5 k
REF+
REF+