L3G4200DTR STMicroelectronics, L3G4200DTR Datasheet
L3G4200DTR
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L3G4200DTR
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L3G4200DTR Summary of contents
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... Appliances and robotics Table 1. Device summary Order code Temperature range (°C) L3G4200D L3G4200DTR December 2010 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ultra-stable three-axis digital output gyroscope Description The L3G4200D is a low-power three-axis angular ...
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Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Pin description ...
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L3G4200D 5.2.2 5.2.3 6 Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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L3G4200D Table 49. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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L3G4200D 1 Block diagram and pin description Figure 1. Block diagram Ω + x,y,z REFERENCE The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing signal is filtered and appears as a digital signal ...
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Block diagram and pin description Table 2. Pin description Pin Figure 3. L3G4200D external low-pass filter values a. Pin 14 PLLFILT maximum voltage level ...
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L3G4200D Table 3. Filter values Parameter Doc ID 17116 Rev 3 Block diagram and pin description Typical value 10 nF 470 nF 10 kΩ 9/42 ...
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Mechanical and electrical characteristics 2 Mechanical and electrical characteristics 2.1 Mechanical characteristics Table 4. Mechanical characteristics @ Vdd = 3 °C, unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Sensitivity change vs. SoDr temperature ...
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L3G4200D 2.2 Electrical characteristics Table 5. Electrical characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Idd Supply current Supply current IddSL (4) in sleep mode Supply current in ...
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Mechanical and electrical characteristics 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 7. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS ...
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L3G4200D 2 2.4 inter IC control interface Subject to general operating conditions for Vdd and Top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) ...
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Mechanical and electrical characteristics 2.5 Absolute maximum ratings Any stress above that listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is ...
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... Stability over temperature and time Thanks to the unique single driving mass approach and optimized design, ST gyroscopes are able to guarantee a perfect match of the MEMS mechanical mass and the ASIC interface, and deliver unprecedented levels of stability over temperature and time. ...
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Main digital blocks 3 Main digital blocks 3.1 Block diagram Figure 6. Block diagram 3.2 FIFO The L3G4200D embeds a 32-slot, 16-bit data FIFO for each of the three output channels: yaw, pitch, and roll. This allows consistent power saving ...
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L3G4200D Figure 7. Bypass mode 3.2.2 FIFO mode In FIFO mode, data from the yaw, pitch, and roll channels are stored in the FIFO. A watermark interrupt can be enabled (I2_WMK bit in CTRL_REG3), which is triggered when the FIFO ...
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Main digital blocks older data as the new data arrives. Programmable watermark level events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3). Stream mode is represented in Figure 9. Stream mode 3.2.4 Bypass-to-stream mode ...
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L3G4200D 3.2.5 Stream-to-FIFO mode In stream-to-FIFO mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A watermark interrupt can be enabled on pin DRDY/INT2, setting the I2_WTM bit in CTRL_REG3, which is triggered when the FIFO ...
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Application hints 4 Application hints Figure 12. L3G4200D electrical connections and external component values 1 (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULAR RATES C1 10nF 10kOhm R2 AM07949V1 Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should ...
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L3G4200D 5 Digital interfaces The registers embedded in the L3G4200D may be accessed through both the I serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the ...
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... LSb is ‘1’ (address 1101001b). Otherwise, if the SDO pin is connected to ground, the LSb value is ‘0’ (address 1101000b). This solution permits the connection and addressing of two different gyroscopes to the same I Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse ...
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L3G4200D Table 15. Transfer when master is writing multiple bytes to slave Master ST Slave Table 16. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W Slave Table 17. Transfer when master ...
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Digital interfaces Figure 13. Read and write protocol CS SPC SDI SDO CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the ...
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L3G4200D The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. Bit 0: READ bit. The value is 1. Bit 1: MS ...
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Digital interfaces Figure 17. Multiple byte SPI write protocol (2-byte example) CS SPC SDI RW MS 5.2.3 SPI read in 3-wire mode 3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit CTRL_REG2. ...
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L3G4200D 6 Output register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 18. Register address map Name Reserved WHO_AM_I Reserved CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 REFERENCE ...
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Output register mapping Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the ...
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L3G4200D 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data ...
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Register description Table 22. DR and BW configuration setting (continued) DR <1:0> Combination of PD, Zen, Yen, Xen are used to set device in different modes (power down ...
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L3G4200D Table 26. High pass filter mode configuration HPM1 Table 27. High pass filter cut off frecuency configuration [Hz] HPCF3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 7.4 CTRL_REG3 ...
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Register description 7.5 CTRL_REG4 (23h) Table 30. CTRL_REG4 register BDU BLE Table 31. CTRL_REG4 description BDU BLE FS1-FS0 ST1-ST0 SIM Table 32. Self test mode configuration ST1 DST sign (absolute value in 7.6 CTRL_REG5 (24h) ...
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L3G4200D Figure 19. INT1_Sel and Out_Sel configuration block diagram LPF1 ADC Table 35. Out_Sel configuration setting Hpen Table 36. INT_SEL configuration setting Hpen LPF2 1 HPF HPen OUT_SEL1 OUT_SEL0 0 0 ...
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Register description 7.7 REFERENCE/DATACAPTURE (25h) Table 37. REFERENCE register Ref7 Ref6 Table 38. REFERENCE register description Ref 7-Ref0 7.8 OUT_TEMP (26h) Table 39. OUT_TEMP register Temp7 Temp6 Table 40. OUT_TEMP register description Temp7-Temp0 7.9 STATUS_REG (27h) Table 41. STATUS_REG register ...
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L3G4200D 7.10 OUT_X_L (28h), OUT_X_H (29h) X-axis angular rate data. The value is expressed as two’s complement. 7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis angular rate data. The value is expressed as two’s complement. 7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis angular ...
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Register description Table 47. FIFO_SRC register description (continued) EMPTY FSS4-FSS1 7.15 INT1_CFG (30h) Table 48. INT1_CFG register AND/OR LIR Table 49. INT1_CFG description AND/OR combination of Interrupt events. Default value: 0 AND/OR (0: OR combination of interrupt events 1: AND ...
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L3G4200D Table 51. INT1_SRC description Interrupt active. Default value (0: no interrupt has been generated; 1: one or more interrupts have been generated high. Default value: 0 (0: no interrupt High event has occurred) ...
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Register description 7.20 INT1_THS_YL (35h) Table 58. INT1_THS_YL register THSR7 THSY6 Table 59. INT1_THS_YL description THSY7 - THSY0 7.21 INT1_THS_ZH (36h) Table 60. INT1_THS_ZH register - THSZ14 Table 61. INT1_THS_ZH description THSZ14 - THSZ9 7.22 INT1_THS_ZL (37h) Table 62. INT1_THS_ZL ...
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L3G4200D Wait =’1’: if signal crosses the selected threshold, the interrupt falls only after the duration has counted number of samples at the selected data rate, written into the duration counter register. Figure 20. Wait disabled Figure 21. Wait enabled ...
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Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ...
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L3G4200D 9 Revision history Table 66. Document revision history Date 01-Apr-2010 03-Sep-2010 22-Dec-2010 Revision 1 Initial release. 2 Complete datasheet review. Section 6: Output register mapping Inserted 3 description. Doc ID 17116 Rev 3 Revision history Changes Section 7: Register ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...