PIC18LF24J10-I/SO Microchip Technology, PIC18LF24J10-I/SO Datasheet - Page 66
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF24J10-I/SO
Manufacturer Part Number
PIC18LF24J10-I/SO
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164332 - MODULE SKT FOR 28SOIC 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 66 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
TABLE 6-3:
DS39682E-page 64
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
TRISE
TRISD
TRISC
TRISB
TRISA
SSP2BUF
LATE
LATD
LATC
LATB
LATA
SSP2ADD
SSP2STAT
SSP2CON1
SSP2CON2
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
MSSP2 Receive Buffer/Transmit Register
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
MSSP2 Address Register in I
PSPIP
PSPIF
PSPIE
OSCFIP
OSCFIF
OSCFIE
SSP2IP
SSP2IF
SSP2IE
WCOL
CSRC
GCEN
GCEN
SPEN
Bit 7
SMP
RD7
RC7
RB7
IBF
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
(2)
(2)
(2)
ACKSTAT
ACKSTAT
BCL2IP
BCL2IF
BCL2IE
SSPOV
CMIP
CMIF
CMIE
ADIP
ADIE
Bit 6
ADIF
OBF
CKE
RD6
RC6
TX9
RX9
RB6
—
—
—
—
—
—
PORTA Data Latch Register (Read and Write to Data Latch)
ADMSK5
2
C™ Slave mode. MSSP2 Baud Rate Reload Register in I
TRISA5
SSPEN
ACKDT
TXEN
SREN
RCIP
RCIF
RCIE
IBOV
Bit 5
RD5
RC5
RB5
RA5
D/A
—
—
—
—
—
—
—
—
—
(3)
PSPMODE
ADMSK4
ACKEN
SYNC
CREN
FREE
TXIP
TXIE
Bit 4
TXIF
CKP
RD4
RC4
RB4
—
—
—
—
—
—
—
—
—
—
P
(3)
ADMSK3
WRERR
ADDEN
SSP1IP
SSP1IE
TRISA3
SENDB
BCL1IP
BCL1IF
BCL1IE
SSP1IF
SSPM3
RCEN
Bit 3
RD3
RC3
RB3
RA3
—
—
—
—
—
—
S
(3)
PORTE Data Latch Register
(Read and Write to Data Latch)
ADMSK2
CCP1IP
CCP1IF
CCP1IE
TRISE2
TRISA2
SSPM2
WREN
BRGH
RE2
FERR
Bit 2
R/W
PEN
RD2
RC2
RB2
RA2
—
—
—
—
—
—
(2)
(3)
2
ADMSK1
C™ Slave mode. See Section 16.4.3.2 “Address
TMR2IP
TMR2IF
TMR2IE
TRISE1
TRISA1
SSPM1
OERR
RE1
TRMT
2
RSEN
Bit 1
RD1
RC1
C Master mode.
RB1
RA1
WR
UA
—
—
—
—
—
—
(2)
(3)
© 2009 Microchip Technology Inc.
TMR1IP
TMR1IE
CCP2IP
CCP2IF
CCP2IE
TMR1IF
TRISE0
TRISA0
SSPM0
RE0
RX9D
TX9D
Bit 0
SEN
SEN
RD0
RC0
RB0
RA0
BF
—
—
—
—
(2)
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
0000 0000
---0 x00-
11-- ----
00-- ----
00-- ----
11-- 1--1
00-- 0--0
00-- 0--0
1111 1111
0000 0000
0000 0000
0000 -111
1111 1111
1111 1111
1111 1111
--1- 1111
xxxx xxxx
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--0- 0000
POR, BOR
Value on
on page:
50, 150,
50, 151,
Details
49, 198
49, 198
49, 205
49, 203
49, 196
49, 195
50, 112
50, 107
50, 104
50, 101
50, 158
50, 110
50, 107
50, 104
50, 101
50, 158
50, 164
48, 163
50, 110
50, 107
50, 104
50, 101
49, 72
49, 74
49, 94
49, 90
49, 92
49, 93
49, 89
49, 91
49, 92
49, 88
49, 91
50, 98
50, 98
50, 98
160
161
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