PIC18LF24J10-I/SO Microchip Technology, PIC18LF24J10-I/SO Datasheet - Page 110
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PIC18LF24J10-I/SO
Manufacturer Part Number
PIC18LF24J10-I/SO
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164332 - MODULE SKT FOR 28SOIC 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 110 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
TABLE 10-9:
DS39682E-page 108
RD0/PSP0/SCK2/
SCL2
RD1/PSP1/SDI2/
SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Legend:
Pin
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTD I/O SUMMARY
Function
SDO2
PSP0
SCK2
PSP1
SDA2
PSP2
PSP3
PSP4
PSP5
PSP6
PSP7
SCL2
SDI2
RD0
RD1
RD2
RD3
SS2
RD4
RD5
P1B
RD6
P1C
RD7
P1D
Setting
TRIS
0
1
x
x
0
1
0
1
0
1
x
x
1
1
1
0
1
x
x
0
0
1
x
x
1
0
1
x
x
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
C/SMB I
C/SMB I
Type
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input.
PSP read data output (LATD<0>); takes priority over port data.
PSP write data input.
SPI clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
I
LATD<1> data output.
PORTD<1> data input.
PSP read data output (LATD<1>); takes priority over port data.
PSP write data input.
SPI data input (MSSP2 module).
I
LATD<2> data output.
PORTD<2> data input.
PSP read data output (LATD<2>); takes priority over port data.
PSP write data input.
SPI data output (MSSP2 module); takes priority over port data.
LATD<3> data output.
PORTD<3> data input.
PSP read data output (LATD<3>); takes priority over port data.
PSP write data input.
Slave select input for MSSP2 (MSSP2 module).
LATD<4> data output.
PORTD<4> data input.
PSP read data output (LATD<4>); takes priority over port data.
PSP write data input.
LATD<5> data output.
PORTD<5> data input.
PSP read data output (LATD<5>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
LATD<6> data output.
PORTD<6> data input.
PSP read data output (LATD<6>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
LATD<7> data output.
PORTD<7> data input.
PSP read data output (LATD<7>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
2
2
2
2
C™ clock output (MSSP2 module); takes priority over port data.
C clock input (MSSP2 module); input type depends on module setting.
C data output (MSSP2 module); takes priority over port data.
C data input (MSSP2 module); input type depends on module setting.
Description
I
2
C™/SMB = I
© 2009 Microchip Technology Inc.
2
C/SMBus input buffer;
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