PIC18LF24J10-I/SO Microchip Technology, PIC18LF24J10-I/SO Datasheet - Page 192
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PIC18LF24J10-I/SO
Manufacturer Part Number
PIC18LF24J10-I/SO
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164332 - MODULE SKT FOR 28SOIC 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 192 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
16.4.17.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to 0. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
FIGURE 16-29:
FIGURE 16-30:
DS39682E-page 190
A low level is sampled on SDAx when SCLx
goes from low level to high level.
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
SDAx
SCLx
RSEN
BCLxIF
S
SSPxIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
T
BRG
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 16-29). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 16-30).
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
T
BRG
© 2009 Microchip Technology Inc.
Cleared in software
Interrupt cleared
in software
‘0’
‘0’
‘0’
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