PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 303
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PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 303 of 318
- Download datasheet (3Mb)
APPENDIX A:
Revision A (November 2005)
Original data sheet for PIC18F1230/1330 devices.
Revision B (February 2006)
Data bank information was updated and a note was
added for calculating the PCPWM duty cycle.
TABLE A-1:
2009 Microchip Technology Inc.
Section 1.0 “Device Overview”
Section 6.0 “Memory Organization”
Section 7.0 “Flash Program Memory”
Section 8.0 “Data EEPROM Memory”
Section 10.0 “I/O Ports”
Section 14.0 “Power Control PWM Module”
Section 15.0 “Enhanced Universal Synchro-
nous Asynchronous Receiver Transmitter
(EUSART)”
Section 16.0 “10-Bit Analog-to-Digital Con-
verter (A/D) Module”
Section 17.0 “Comparator Module”
Section 18.0 “Comparator Voltage Refer-
ence Module”
Section 20.0 “Special Features of the CPU”
Section 22.0 “Instruction Set Summary”
Section 23.0 “Electrical Characteristics”
Section Name
SECTION REVISION HISTORY
REVISION HISTORY
Updated Table 1-2
Updated Table 6-2
Updated Section 7.2.4 “Table Pointer Boundaries”, Figure 7-3
Updated Section 8.2 “EECON1 and EECON2 Registers”,
Section 8.8 “Using the Data EEPROM”
Updated Section 10.2 “PORTB, TRISB and LATB Registers”
Updated Register 14-6, Section 14.11.2 “Output Polarity Con-
trol”
Updated Register 15-3, Section 15.1 “Baud Rate Generator
(BRG)”, Table 15-2, Section 15.1.3 “Auto-Baud Rate Detect”,
Section 15.2 “EUSART Asynchronous Mode”, Table 15-5,
Table 15-6, Section 15.3 “EUSART Synchronous Master
Mode”, Figure 15-11, Table 15-7, Figure 15-13, Table 15-8,
Table 15-9, Table 15-10
Updated Register 16-2
Updated Figure 17-2
Updated Section 18.1 “Configuring the Comparator Voltage
Reference”, Register 18-1, Figure 18-1
Updated Register 20-6, Register 20-13, Register 20-14
Updated Table 22-2
Updated Table 23-1, Figure 23-3, Table 23-2, Table 23-3, Table 23-
4, Table 23-5, Table 23-6, Table 23-8, Table 23-14, Table 23-15
Revision C (March 2007)
Updated Section 23.0 “Electrical Characteristics”
and Section 24.0 “Packaging Information”.
Revision D (November 2009)
Updated LIN 1.2 to LIN/J2602 throughout document
along with minor corrections throughout document.
Added the PIC18LF1230 and PIC18LF1330 devices.
Refer to Table A-1 for additional revision history.
PIC18F1230/1330
Update Description
DS39758D-page 303
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