PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 190
![Microcontroller](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 190 of 318
- Download datasheet (3Mb)
PIC18F1230/1330
19.5
In many applications, the ability to detect a drop below
a particular threshold is desirable.
For general battery applications, Figure 19-3 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage
V
interrupt could cause the execution of an ISR, which
would allow the application to perform “housekeeping
tasks” and perform a controlled shutdown before the
device voltage exits the valid operating range at T
The LVD, thus, would give the application a time win-
dow, represented by the difference between T
to safely exit.
FIGURE 19-3:
TABLE 19-1:
DS39758D-page 190
LVDCON
INTCON
PIR2
PIE2
IPR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the LVD module.
A
, the LVD logic generates an interrupt at time T
Name
Legend:
V
V
A
B
Applications
V
V
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIF
OSCFIE
OSCFIP
A
B
Bit 7
= LVD trip point
= Minimum valid device
REGISTERS ASSOCIATED WITH LOW-VOLTAGE DETECT MODULE
—
operating voltage
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
Time
Bit 6
—
—
—
—
T
A
T
IRVST
B
Bit 5
—
—
—
A
and T
A
. The
LVDEN
INT0IE
B
B
EEIE
EEIP
Bit 4
EEIF
.
,
19.6
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
19.7
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
LVDL3
RBIE
Bit 3
—
—
—
Operation During Sleep
Effects of a Reset
TMR0IF
LVDL2
LVDIF
LVDIE
LVDIP
Bit 2
INT0IF
LVDL1
2009 Microchip Technology Inc.
Bit 1
—
—
—
LVDL0
RBIF
Bit 0
—
—
—
on Page:
Values
Reset
48
47
49
49
49
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