PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 293
![Microcontroller](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 293 of 318
- Download datasheet (3Mb)
FIGURE 23-13:
TABLE 23-15: A/D CONVERSION REQUIREMENTS
2009 Microchip Technology Inc.
130
131
132
135
136
Note 1:
Param
No.
Note 1:
A/D CLK
A/D DATA
SAMPLE
2:
3:
4:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
Q4
(1)
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
(3)
9
to V
SS
8
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
or V
OLD_DATA
SS
7
(2)
SAMPLING STOPPED
to V
. . .
CY
DD
is added before the A/D clock starts. This allows the SLEEP instruction
). The source impedance (R
CY
. . .
130
cycle.
131
Min
0.7
1.4
1.4
0.2
—
—
11
—
2
(Note 4)
25.0
25.0
PIC18F1230/1330
Max
12
—
—
1
3
1
(1)
(1)
Units
T
s
s
s
s
s
s
AD
S
0
) on the input channels is 50.
T
V
T
A/D RC mode
V
-40C to +85C
OSC
OSC
DD
DD
AD
= 2.0V,
= 2.0V, A/D RC mode
based, V
based, V
clock divider.
DONE
NEW_DATA
Conditions
DS39758D-page 293
T
CY
REF
REF
3.0V
full range
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