PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 142
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PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 142 of 318
- Download datasheet (3Mb)
PIC18F1230/1330
FIGURE 14-23:
14.11.3
The PWMPIN Configuration bit determines the PWM
output pins to be PWM output pins, or digital I/O pins,
after the device comes out of Reset. If the PWMPIN
Configuration bit is unprogrammed (default), the
PWMEN2:PWMEN0 control bits will be cleared on a
device Reset. Consequently, all PWM outputs will be
tri-stated and controlled by the corresponding PORT
and TRIS registers. If the PWMPIN Configuration bit is
programmed low, the PWMEN2:PWMEN0 control bits
will be set to ‘100’ on a device Reset:
All PWM pins will be enabled for PWM output and will
have the output polarity defined by the HPOL and
LPOL Configuration bits.
14.12 PWM Fault Input
There is one Fault input associated with the PWM
module. The main purpose of the input Fault pin is to
disable the PWM output signals and drive them into an
inactive state. The action of the Fault input is performed
DS39758D-page 142
Note:
PWM OUTPUT PIN RESET STATES
PWM Signal from Module
PWM Pin Enable
Data Bus
WR PORT
WR TRIS
RD TRIS
RD PORT
I/O pin has protection diodes to V
PWM I/O PIN BLOCK DIAGRAM
Data Latch
TRIS Latch
D
D
CK
CK
Q
Q
Q
Q
DD
and V
SS
. PWM polarity selection logic not shown for clarity.
1
0
directly in hardware so that when a Fault occurs, it can
be managed quickly and the PWMs outputs are put into
an inactive state to save the power devices connected
to the PWMs.
The PWM Fault input is FLTA, which can come from
I/O pins, the CPU or another module. The FLTA pin is
an active-low input so it is easy to “OR” many sources
to the same input.
The FLTCONFIG register (Register 14-8) defines the
settings of the FLTA input.
14.12.1
By setting the bit FLTAEN in the FLTCONFIG register,
the corresponding Fault input is enabled. If FLTAEN bit
is cleared, then the Fault input has no effect on the
PWM module.
Q
Note:
EN
D
The inactive state of the PWM pins is
dependent on the HPOL and LPOL Con-
figuration bit settings, which define the
active and inactive state for PWM outputs.
FAULT PIN ENABLE BIT
V
V
P
N
DD
SS
2009 Microchip Technology Inc.
TTL or
Schmitt
Trigger
I/O pin
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