PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 186

• Manufacturer Part Number: PIC18F4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

comparator
PIC18F2480/2580/4480/4580
17.4.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned off), both switches may be on for a short period of
time until one switch completely turns off. During this
brief interval, a very high current (shoot-through current)
may flow through both power switches, shorting the
bridge supply. To avoid this potentially destructive
shoot-through current from flowing during switching,
turning on either of the power switches is normally
delayed to allow the other switch to completely turn off.
In the Half-Bridge Output mode, a digitally program-
mable, dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transi-
tion from the non-active state to the active state (see
Figure 17-4 for illustration). Bits, PDC<6:0< of the
ECCP1DEL register (Register 17-2), set the delay
period in terms of microcontroller instruction cycles
(T
PIC18F2X80 devices, as the standard CCP module
does not support half-bridge operation.
17.4.7
When the CCP1 is programmed for any of the Enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the Enhanced PWM output pins into a defined shutdown
state when a shutdown event occurs.
A shutdown event can be caused by either of the
RB0/INT0/FLT0/AN10 pin, or any combination of these
three sources. The comparators may be used to monitor
a voltage input proportional to a current being monitored
in the bridge circuit. If the voltage exceeds a threshold,
the comparator switches state and triggers a shutdown.
Alternatively, a digital signal on the INT0 pin can also
trigger a shutdown. The auto-shutdown feature can be
disabled by not selecting any auto-shutdown sources.
The auto-shutdown sources to be used are selected
using the ECCPAS<2:0> bits (ECCP1AS<6:4>).
DS39637D-page 186
CY
Note:
or 4 T
PROGRAMMABLE DEAD-BAND
DELAY
Programmable dead-band delay is not
implemented in PIC18F2X80 devices with
standard CCP modules.
ENHANCED PWM AUTO-SHUTDOWN
OSC
modules,
). These bits are not available on
a
low
level
on
the
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified by the PSSAC<1:0> and PSS1BD<1:0> bits
(ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/P1D)
may be set to drive high, drive low or be tri-stated (not
driving). The ECCPASE bit (ECCP1AS<7>) is also set to
hold the Enhanced PWM outputs in their shutdown
states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
If the dead-band delay value is increased
after the dead-band time has elapsed, that
new value takes effect immediately. This
happens even if the PWM pulse is high
and can appear to be a glitch. Dead-band
values must be changed during the
dead-band time or before ECCP is active
© 2009 Microchip Technology Inc.