PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 148

• Manufacturer Part Number: PIC18F4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39637D-page 148
PORTE
LATE
TRISE
ADCON1
CMCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
MCLR/V
Legend:
Name
(2)
Pin Name
2:
3:
(3)
PP
(3)
(3)
/RE3
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both PIC18F2X80 and PIC18F4X80 devices. All other bits are
implemented only when PORTE is implemented (i.e., PIC18F4X80 devices).
These registers are unimplemented on PIC18F2X80 devices.
PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input
C2OUT
Bit 7
IBF
—
—
—
PORTE I/O SUMMARY
Function
C1OUT
C2OUT
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
V
WR
RD
CS
PP
C1OUT
Bit 6
OBF
—
—
—
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRIS Buffer
VCFG1
C2INV
IBOV
Bit 5
0
1
1
1
0
1
1
1
0
0
1
1
1
0
x
x
1
—
—
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
ST
ST
ST
ST
ST
PSPMODE
VCFG0
C1INV
Bit 4
LATE<0> data output.
PORTE<0> data input.
PSP read enable input.
A/D Input Channel 5. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
LATE<1> data output.
PORTE<1> data input.
PSP write enable input.
A/D Input Channel 6. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
Comparator 1 output.
LATE<2> data output.
PORTE<2> data input.
PSP chip select input.
A/D Input Channel 7. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
Comparator 2 output.
External Reset input. Disabled when MCLRE Configuration bit is ‘1’.
High-voltage detection; used by ICSP™ operation.
PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’.
—
—
RE3
PCFG3
Bit 3
CIS
—
—
(1,2)
LATE Output Latch Register
TRISE2
PCFG2
Bit 2
CM2
RE2
Description
TRISE1
PCFG1
Bit 1
CM1
© 2009 Microchip Technology Inc.
RE1
TRISE0
PCFG0
Bit 0
CM0
RE0
on Page:
Values
Reset
58
58
58
56
57