PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 181

• Manufacturer Part Number: PIC18F4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 17-2:
FIGURE 17-3:
© 2009 Microchip Technology Inc.
Relationships:
• Period = 4 * T
• Duty Cycle = T
• Delay = 4 * T
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable Dead-Band Delay”).
00
10
01
11
00
10
01
11
(Single Output)
ECCP1CON
(Half-Bridge)
(Full-Bridge,
(Full-Bridge,
Forward)
Reverse)
(Single Output)
<7:6>
ECCP1CON
(Half-Bridge)
(Full-Bridge,
(Full-Bridge,
Forward)
Reverse)
<7:6>
OSC
OSC
OSC
* (ECCP1DEL<6:0>)
* (PR2 + 1) * (TMR2 Prescale Value)
* (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value)
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
SIGNAL
SIGNAL
PIC18F2480/2580/4480/4580
0
Delay
0
Delay
(1)
Cycle
(1)
Duty
Cycle
Duty
Delay
Period
Delay
Period
(1)
(1)
DS39637D-page 181
PR2 + 1
PR2 + 1